Senior DFT engineer

Broadcom; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Broadcom seeks a Design-for-Test (DFT) Engineer to advance DFT across complex hierarchical SoC/ASIC designs. You will insert DFT, verify with SSN-based methods, and collaborate with Physical design and ATE teams to ensure first-pass silicon success.

Role requires hands-on DFT insertion, SSN validation, ATPG generation, and verilog/gate-level verification. Strong scripting skills (TCL/Python/Perl) are essential for automation and pattern management.

Qualifications

• 3+ years in DFT design and verification.
• Strong understanding of scan-based test architectures and hierarchical DFT.
• Hands-on with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation and fault coverage analysis.
• Familiarity with ATE test flows and pattern validation on test platforms.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC/ASIC designs and top-level integration.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent architectures.
• Validate SSN topology, balance scan chains, and manage clock domain crossings.
• Integrate Boundary Scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults.
• DFT verification including verilog/gate-level simulation.
• Collaborate with cross-functional teams to resolve DFT/testing timing challenges.
• Work with ATE engineers to prepare timing and pattern files (STIL/WGL) for tester readiness.
• Support silicon bring-up and production test debugging through Diagnostics and failure analysis.

Skills

DFT design

Verification

ATPG generation

Scripting (TCL, Python, Perl)

Boundary scan (IEEE 1149.x)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Siemens Tessent

Job description

Job Description

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs. This position involves hands‑on work in DFT insertion, and comprehensive DFT verification to ensure first-pass silicon success. You will collaborate closely with Physical design team, ATE test teams to develop efficient, high-quality test strategies aligned with industry standards.

Job Description

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs. This position involves hands‑on work in DFT insertion, and comprehensive DFT verification to ensure first-pass silicon success. You will collaborate closely with Physical design team, ATE test teams to develop efficient, high-quality test strategies aligned with industry standards.

Key Responsibilities

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including both block-level and top-level DFT integration.


• Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.


• Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings.


• Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.


• Generate and analyze ATPG patterns for stuck‑at, transition, and path delay faults to ensure optimal test coverage.


• Perform DFT verification, including verilog / gate level simulation


• Work closely with cross‑functional teams to resolve DFT/testing timing challenges.


• Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.


• Support silicon bring‑up, production test debugging through Diagnostics and failure analysis.

Qualifications

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field.


• Minimum 3 years of experience in DFT design and verification (5+ years preferred for senior roles).


• Strong understanding of scan‑based test architectures, test compression, and hierarchical DFT implementation.


• Hands‑on experience with DFT tools such as Siemens Tessent.


• Proficiency in ATPG generation, fault coverage analysis, and gate‑level DFT verification.


• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.


• Strong scripting skills in TCL, Perl, or Python for DFT automation.

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