Senior DFT Architect for SoC/ASIC Test & Verification

Broadcom Inc.; Singapore; Presencial; SGD 90 000 - 150 000; Tempo integral

Resumo da oferta

Broadcom Inc. is seeking a Design-for-Test (DFT) Engineer to join the SoC/ASIC DFT development team.

You will implement and verify DFT solutions across complex hierarchical designs, performing hands-on DFT insertion and comprehensive verification for first-pass silicon success. In this role, you will collaborate with Physical Design and ATE test teams to develop efficient test strategies, generate ATPG patterns, and validate timing and pattern files for tester compatibility and production

Qualificações

• Bachelor's or master's degree in electrical/computer engineering or related field.
• 3+ years in DFT design and verification; 5+ years for senior roles.
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT.

Responsabilidades

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including block- and top-level DFT integration.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent architectures.
• Validate SSN topology, manage scan chain balancing and clock domain crossings.
• Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults.
• Perform DFT verification, including verilog/gate-level simulation.
• Collaborate with cross-functional teams to resolve DFT/testing timing challenges.
• Prepare and validate timing and pattern files (STIL/WGL) for tester compatibility.

Conhecimentos

TCL scripting

Python scripting

Perl scripting

DFT automation

Formação académica

Bachelor's or Master's in Electrical/Computer Engineering

Ferramentas

Siemens Tessent

Advantest

Teradyne

Descrição da oferta de emprego

Broadcom Inc. is seeking a Design-for-Test (DFT) Engineer to join the SoC/ASIC DFT development team.

You will implement and verify DFT solutions across complex hierarchical designs, performing hands-on DFT insertion and comprehensive verification for first-pass silicon success. In this role, you will collaborate with Physical Design and ATE test teams to develop efficient test strategies, generate ATPG patterns, and validate timing and pattern files for tester compatibility and production