DFT Engineer

JUMPSTART DISRUPTIVE INNOVATIONS PTE. LTD.; Singapore; On-site; SGD 100,000 - 156,000; Full time

Job summary

Jumpstart Disruptive Innovations Pte. Ltd. is seeking an experienced DFT Engineer to drive testability for digital and mixed-signal IP. You will implement DFT for scan logic, IJTAG, MBIST, and logic BIST, and generate ATPG patterns for production testing.

The role requires 3+ years in DFT, a Bachelors in Electrical or Computer Engineering, and strong HDL knowledge with UNIX/Linux and scripting (TCL, cshell, Perl). Teamwork and clear communication are essential.

Qualifications

• Min 3 years of related working experience.
• Bachelor degree or equivalent in Electrical or Computer Engineering.
• Familiar with HDL design language.
• Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell, Perl).
• Knowledge of ASIC design is a must, and ATE test is a plus.
• Strong problem solving skills.
• Team player with strong communication skills.

Responsibilities

• DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST.
• Analysis to improve the testability of Digital design at Block and chip level.
• Implementation of DFT logics for Digital and Mixed Signal IP.
• Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern.
• Perform ATPG verification and simulation playback.
• Deliver high quality ATE patterns for production ATE testing.
• Provide test pattern support to ATE engineering team for First Proto bring up and failure analysis in the use of ATPG test and scan/debug features.

Skills

DFT engineering

ATPG

HDL design language

UNIX/Linux

Scripting (TCL, cshell, Perl)

ASIC design knowledge

Team communication

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

TCL

Perl

cshell

ATPG tooling

Job description

Job Description & Requirements

We are seeking an experienced DFT Engineer. The successful candidate will be responsible of:

• DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST
• Analysis to improve the testability of Digital design at Block and chip level.
• Implementation of DFT logics for Digital and Mixed Signal IP.
• Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern.
• Perform ATPG verification and simulation playback
• Deliver high quality ATE patterns for production ATE testing
• Provide test pattern support to ATE engineering team for First Proto bring up and
• failure analysis in the use of ATPG test and scan/debug features

Experience

• Min 3 years of related working experience
• Bachelor degree or equivalent in Electrical or Computer Engineering
• Familiar with HDL design language
• Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell, Perl)
• Knowledge of ASIC design is a must, and ATE test is a plus
• Strong problem solving skills
• Team player with strong communication skills