Senior DFT Engineer, SoC/ASIC Test Architect

Broadcom; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Broadcom seeks a Design-for-Test (DFT) Engineer to advance DFT across complex hierarchical SoC/ASIC designs. You will insert DFT, verify with SSN-based methods, and collaborate with Physical design and ATE teams to ensure first-pass silicon success.

Role requires hands-on DFT insertion, SSN validation, ATPG generation, and verilog/gate-level verification. Strong scripting skills (TCL/Python/Perl) are essential for automation and pattern management.

Qualifications

• 3+ years in DFT design and verification.
• Strong understanding of scan-based test architectures and hierarchical DFT.
• Hands-on with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation and fault coverage analysis.
• Familiarity with ATE test flows and pattern validation on test platforms.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC/ASIC designs and top-level integration.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent architectures.
• Validate SSN topology, balance scan chains, and manage clock domain crossings.
• Integrate Boundary Scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults.
• DFT verification including verilog/gate-level simulation.
• Collaborate with cross-functional teams to resolve DFT/testing timing challenges.
• Work with ATE engineers to prepare timing and pattern files (STIL/WGL) for tester readiness.
• Support silicon bring-up and production test debugging through Diagnostics and failure analysis.

Skills

DFT design

Verification

ATPG generation

Scripting (TCL, Python, Perl)

Boundary scan (IEEE 1149.x)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Siemens Tessent

Job description

Broadcom seeks a Design-for-Test (DFT) Engineer to advance DFT across complex hierarchical SoC/ASIC designs. You will insert DFT, verify with SSN-based methods, and collaborate with Physical design and ATE teams to ensure first-pass silicon success.

Role requires hands-on DFT insertion, SSN validation, ATPG generation, and verilog/gate-level verification. Strong scripting skills (TCL/Python/Perl) are essential for automation and pattern management.