Senior DFT engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a Design-for-Test (DFT) Engineer to join the SoC/ASIC DFT development team in Singapore.

The role involves hands-on DFT insertion and comprehensive verification to ensure first-pass silicon success, collaborating with Physical design and ATE test teams to develop efficient test strategies. You will implement DFT architectures, perform scan insertion, test compression, and verify SSN topology, while generating ATPG patterns and

Qualifications

• Bachelor’s or Master’s degree in electrical/computer engineering or related field.
• 3+ years in DFT design and verification (5+ years for senior roles).
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.
• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
• Strong scripting skills in TCL, Perl, or Python for DFT automation.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC/ASIC designs (block and top-level).
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent.
• Validate SSN topology, manage scan chain balancing and clock domain crossings.
• Integrate Boundary scan and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults.
• Perform DFT verification via Verilog/gate-level simulations.
• Collaborate with cross-functional teams to address DFT/testing timing challenges.
• Prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.
• Support silicon bring-up and production test debugging.

Skills

DFT architecture

Verification

ATPG generation

Scripting (TCL, Python, Perl)

Boundary scan (IEEE 1149.x)

SSN compression architectures

Scan insertion

Clock domain crossings

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Siemens Tessent

Job description

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs. This position involves hands-on work in DFT insertion, and comprehensive DFT verification to ensure first-pass silicon success. You will collaborate closely with Physical design team, ATE test teams to develop efficient, high-quality test strategies aligned with industry standards.

Key Responsibilities

1. a) Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including both block-level and top-level DFT integration.

2. b) Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.

3. c) Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings.

4. d) Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.

5. e) Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure optimal test coverage.

6. f) Perform DFT verification, including verilog / gate level simulation

7. g) Work closely with cross-functional teams to resolve DFT/testing timing challenges.

8. i) Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.

9. j) Support silicon bring-up, production test debugging through Diagnostics and failure analysis.
   

Qualifications

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field.

• Minimum 3 years of experience in DFT design and verification (5+ years preferred for senior roles).

• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.

• Hands-on experience with DFT tools such as Siemens Tessent.

• Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.

• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.

• Strong scripting skills in TCL, Perl, or Python for DFT automation.