Senior ASIC/SoC Verification Engineer & Automation Lead

TetraMem Inc.; Singapore; On-site; SGD 80,000 - 180,000; Full time

Benefits offered by this job

Equal Opportunity Employer

Accommodation for candidates

Job summary

TetraMem Inc. is seeking an experienced verification engineer in Singapore to define and implement detailed test plans for SoC verification. You will build automation infrastructure and develop reusable testbenches for both block and system levels, driving coverage closure and debugging RTL and post-P&R issues.

You will mentor engineers, lead regression strategies, and coordinate with design teams to ensure robust pre-silicon verification and post-silicon support.

Qualifications

• Proficient in UVM/OVM, semiformal verification and assertion-based methods.
• Experience building verification infra, test plans, coverage closure and debug.
• Strong scripting in Python/Perl/TCL/Shell; Proficient in Verilog/SystemVerilog.

Responsibilities

• Define, document and implement detailed test plans for SoC verification.
• Build and maintain automation verification infrastructure for SoC architecture, function and performance.
• Develop reusable testbenches, constrained-random and directed tests for block and system levels.

Skills

UVM/OVM

Test planning

Debugging

Verification leadership

Education

MS or PhD in Electrical/Computer Engineering

Tools

Verilog

SystemVerilog

Python

C/C++

SystemC

Job description

TetraMem Inc. is seeking an experienced verification engineer in Singapore to define and implement detailed test plans for SoC verification. You will build automation infrastructure and develop reusable testbenches for both block and system levels, driving coverage closure and debugging RTL and post-P&R issues.

You will mentor engineers, lead regression strategies, and coordinate with design teams to ensure robust pre-silicon verification and post-silicon support.