Design Verification Engineer - ASIC/SoC (UVM, SystemVerilog)

Mediatek Singapore Pte Ltd; Singapore; On-site; SGD 78,000 - 123,000; Full time

Job summary

MediaTek Incorporated in Singapore is seeking engineers to contribute to ASIC DV efforts for IP/SoC verification. You will design verification plans and environments, and implement IP/testbench components with UVM, SystemVerilog, Verilog and SystemC.

Join a team focused on challenging projects across WiFi, 5G, AR/VR, AI and cloud networking, with opportunities for continuous learning and professional growth at the One North campus in Singapore.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• Dedication to continuous self-developing and learning new technologies.
• Good knowledge of chip design flow and EDA tools.
• Strong coding skills in C/C++, Perl, Python, and Unix/Linux shell.

Responsibilities

• Module/IP/SOC design verification.
• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization-based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Formal verification.
• Verification automation flow.

Skills

C/C++

Perl

Python

Unix/Linux shell

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering or related

Tools

UVM

SystemVerilog

Verilog

SystemC

Job description

MediaTek Incorporated in Singapore is seeking engineers to contribute to ASIC DV efforts for IP/SoC verification. You will design verification plans and environments, and implement IP/testbench components with UVM, SystemVerilog, Verilog and SystemC.

Join a team focused on challenging projects across WiFi, 5G, AR/VR, AI and cloud networking, with opportunities for continuous learning and professional growth at the One North campus in Singapore.