Senior DFT Engineer - SoC/ASIC Test Architect

Broadcom, Inc.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Broadcom, Inc. in Singapore is seeking a Senior DFT engineer to design and verify DFT solutions for complex SoC/ASIC hierarchies. You will insert scans, manage test compression, and verify with ATPG patterns.

Collaboration with Physical Design and ATE teams, and support silicon bring-up and production test debugging. Requires hands-on experience with Tessent and SSN, plus TCL/Python scripting.

Qualifications

• Bachelor's or master's degree in electrical engineering, computer engineering, or related field.
• Minimum 3 years of experience in DFT design and verification (5+ years for senior).
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.
• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
• Strong scripting skills in TCL, Perl, or Python for DFT automation.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including block-level and top-level DFT integration.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.
• Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings.
• Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure optimal test coverage.
• Perform DFT verification, including verilog / gate level simulation
• Work closely with cross-functional teams to resolve DFT/testing timing challenges.
• Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.
• Support silicon bring-up, production test debugging through Diagnostics and failure analysis.

Skills

DFT design

DFT verification

ATPG generation

Fault coverage

Scripting (TCL)

Scripting (Python)

Scripting (Perl)

Boundary scan

Education

Bachelor's or Master's in EE/CE

Tools

Siemens Tessent

Advantest

Teradyne

Job description

Broadcom, Inc. in Singapore is seeking a Senior DFT engineer to design and verify DFT solutions for complex SoC/ASIC hierarchies. You will insert scans, manage test compression, and verify with ATPG patterns.

Collaboration with Physical Design and ATE teams, and support silicon bring-up and production test debugging. Requires hands-on experience with Tessent and SSN, plus TCL/Python scripting.