Design Verification Engineer — IP/SoC, UVM & Low Power

MediaTek; Singapore; Sur place; SGD 70 000 - 110 000; Plein temps

Résumé du poste

MediaTek is seeking a verification engineer in Singapore to contribute to module/IP/SOC verification, develop test plans, and build robust verification environments. You will implement randomization-based coverage driven verification, close functional and code coverage, and perform hands-on debugging with UVM, SystemVerilog, Verilog and SystemC.

The team focuses on cutting-edge verification methodologies for WiFi, 5G, AR/VR, AI, and cloud networking.

Qualifications

• > Bachelor's degree in Electrical Engineering, Computer Engineering or related.
• > Strong motivation to continuously learn new technologies.
• > Good knowledge of chip design flow and EDA tools.
• > Strong coding skills in C/C++, Perl, Python, and Unix/Linux shell.

Responsabilités

• Module/IP/SOC design verification.
• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization-based coverage driven verification methodology.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Formal verification.
• Verification automation flow.

Connaissances

C/C++

Perl

Python

Unix/Linux shell

Formation

Bachelor's degree in Electrical Engineering or Computer Engineering

Outils

UVM

SystemVerilog

Verilog

SystemC

Description du poste

MediaTek is seeking a verification engineer in Singapore to contribute to module/IP/SOC verification, develop test plans, and build robust verification environments. You will implement randomization-based coverage driven verification, close functional and code coverage, and perform hands-on debugging with UVM, SystemVerilog, Verilog and SystemC.

The team focuses on cutting-edge verification methodologies for WiFi, 5G, AR/VR, AI, and cloud networking.