R&D Engineer Adv Tech Dev (PKE) / Sr. Staff

SwiftCruit; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom is seeking a senior IC packaging professional to lead development for next‑generation silicon node packages in Singapore. You will collaborate with IC design, system, and thermal teams to define substrate solutions, BOMs and manufacturing plans, ensuring performance and reliability.

The role requires deep CPI/SI/PI knowledge, Cadence APD proficiency, and hands‑on experience with flip‑chip, MCMs and 2.5D/3DIC concepts.

Qualifications

• BS/MS/PhD in STEM or closely related engineering field.
• Experience with IC packaging and advanced node programs is preferred.
• Strong understanding of signal integrity and power integrity concepts.
• Experience with Cadence APD for substrate design.
• Ability to read mechanical drawings (GD&T) and work with cross-functional teams.

Responsibilities

• Design custom packages with IC design, system design, package SI/PI & thermal teams.
• Ensure packages meet CPI, SI/PI and thermal requirements for advanced node silicon products.
• Manage IC packaging from concept through high volume production.
• Define assembly BOM, process, troubleshoot packaging issues, support new technology adoption.
• Productize newly developed technologies into high volume manufacturing (HVM).
• Create package design documentation and assembly instructions.
• Interface with QA and customers to resolve quality issues; coordinate with suppliers for qualification and ramp.
• Support NPI bring-up, package qualification, and sustainment in production and multi-source activities.

Skills

Cadence APD

Signal integrity

Power integrity

Flip-chip packaging

2.5D/3DIC

CPI concepts

Project management

Leadership

GD&T reading

Education

BS/MS/PhD in STEM/Material Science/Electrical/Mechanical Engineering

Tools

Cadence APD

SAP/mSAP

PSPI with Cu RDL

Job description

Job Description

Work with business unit marketing and IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability for new advanced silicon node products (5nm, 3nm, 2nm and beyond)

• Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages
• Ensure designed packages meet CPI, SI/PI, and stringent thermal requirements (1000sW+) of advanced node cutting edge silicon products
• Research, develop, and productize new materials such as TIM, build-up-film, underfill etc. in support advanced node silicon (5nm & 3/2nm) POR definition
• Manage IC packaging activity from concept through development, qualification and high volume production
• Be a specialist and able to define assembly BOM, process, troubleshoot, support on packaging issues on new advanced technology
• Implement, fine-tune, and productize newly developed technologies into HVM
• Create package design documentation and assembly instructions
• Work close with QA and customers to resolve quality issues
• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp
• Interface with other operations functional groups such as product engineering, foundry, test, and QA
• Participate in package technology development and/or other business productivity projects which have broad team impact (e.g. assembly process enhancement, new TIM material development etc.)
• Interface with tier #1 external customers for custom ASIC programs or as needed for development support, quality and/or other issue resolution
• Support NPI bring-up, pkg qual, and sustain support in production + multi-source activities for capacity, cost, & manufacturing flexibility needs

Job Requirements

• Education: BS/MS/PHD in STEM/Material Science/Electrical/Mechanical Engineering
• Experience: BS +8 years of experience or MS +6 years of experience or PhD + 3 years of experience is required
• Deep understanding of signal integrity and power integrity concepts such as characteristic impedance, s-parameters (RL, IL, FEXT/NEXT etc.), power plane impedance profile requirements and optimization etc.
• Strong authority on Cadence APD for custom substrate design
• Hands-on expertise of advanced and new assembly processes for flipchip, MCM packages, and 2.5D for advanced node silicon products (5nm, 3/2nm and beyond)
• Good understanding of materials as related to Chip Packaging Interaction (CPI)
• Familiarity with wafer BEOL as related to CPI (top metal, AP, passivation, UBM, bumping etc.)
• Knowledge of advanced substrate manufacturing/process is a must (e.g. SAP/mSAP, PSPI w/ Cu RDL etc.)
• In depth knowledge of failure analysis techniques on advanced node silicon (5nm, 3/2nm etc.) products with ELK and MiM structures
• Conceptual knowledge of package cost structure
• Strong project management, communication and leadership skills
• Must have knowledge of GD&T and be able to read/comprehend mechanical drawings
• Good understanding of manufacturing and quality engineering fundamentals (DOE, process capability indices, etc.)
• Job requirements are broad; the candidate must be able to expand and grow in multiple disciplines (manufacturing/quality, materials, electrical, thermal, and mechanical)
• Track record of innovation and subject matter expertise through journal publications and/or patent awards is desired
• Familiarity with advanced technologies such as 2.5D, 3DIC, glass substrate etc.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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