Package Design Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED in Singapore is seeking an experienced package design engineer for advanced ASICs particularly in high-speed SerDes and RF communications. This role involves overall design responsibility of package designs, focusing on manifold aspects like manufacturability and reliability.

The ideal candidate should hold a B.Eng or M.Eng in Electrical Engineering or a similar field, with significant experience in flip-chip-BGA package design. Collaborating in a global team is essential.

Qualifications

• 5+ years of experience in flip-chip-BGA package design including high-speed SerDes.
• Knowledge of package-level signal integrity and power integrity.
• Good organizational skills to manage multiple design projects.

Responsibilities

• Overall design responsibility for ASIC package designs.
• Schedule, prioritize, & track work across multiple projects.
• Collaborate with team members for co-design and package models.

Skills

Package design for flip-chip BGA

Signal integrity

Power integrity

Task management

Cadence APD

Education

B.Eng in Electrical Engineering or similar

M.Eng in Electrical Engineering or similar

Job description

Broadcom is seeking an experienced package design engineer for complex flip‑chip‑BGA packages for industry‑leading ASICs with high‑speed SerDes and RF/microwave communications A/D‑D/A converters (ADC & DAC). You will be part of a worldwide R&D team developing high‑performance package designs for ASICs used in artificial intelligence (AI), networking, high‑performance computing (HPC), and 5G base stations. These designs include SerDes at 112G and higher, RF/Microwave ADC/DAC, DDR and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design.

RESPONSIBILITIES

• Overall design responsibility for ASIC package designs (layout/routing), including aspects of impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
• Package Design of critical high frequency/datarate structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, & track your work across multiple projects simultaneously
• General flip‑chip BGA package design & engineering

EDUCATION/EXPERIENCE & REQUIREMENTS

• B.Eng (EE/EEE) or similar field and 5+ years’ experience in flip‑chip‑BGA package design, including high‑speed SerDes
• M.Eng (EE/EEE) or similar field and 3+ years’ experience in flip‑chip‑BGA package design, including high‑speed SerDes
• Knowledge of package‑level signal integrity and power integrity, to apply to package designs
• Cadence APD (Allegro Package Designer) experience is preferred. Equivalent tool is OK.
• Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (vendor) designers.
• Good organizational and task management skills to manage multiple package design projects.

PREFERRED EDUCATION/EXPERIENCE & REQUIREMENTS

• B.Eng (EE/EEE) or similar field and 8+ years’ experience in flip‑chip‑BGA package design, including high‑speed SerDes preferred.
• M.Eng (EE/EEE) or similar field and 6+ years’ experience in flip‑chip‑BGA package design, including high‑speed SerDes preferred.