Junior ASIC Timing & Analysis Engineer

Black Sesame Technologies (Singapore) Pte Ltd; Singapore; Presencial; SGD 45.000 - 69.000; Jornada completa

Descripción de la vacante

Black Sesame Technologies is seeking fresh graduates to join as ASIC STA Engineers. This entry-level role focuses on timing closure, verification, constraints (SDC), and timing analysis to ensure chip performance and integrity.

You will work closely with front-end and back-end teams to drive PPA targets and learn the ASIC design flow. The position emphasizes learning, collaboration, and proactive problem-solving while contributing to innovative projects in ASIC timing analysis and design

Formación

• Master’s degree or higher in Electronics Engineering, Computer Science, or a related field.
• Fundamental knowledge of ASIC timing analysis and synthesis.
• Familiarity with the ASIC development process and design flow.
• Proficiency in programming languages such as Perl, Tcl, Python, or similar.
• Strong communication skills and collaborative, proactive problem-solving attitude.

Responsabilidades

• Oversee timing closure at the block level throughout the project lifecycle to ensure design integrity.
• Develop and maintain methodologies for timing verification and closure.
• Collaborate with designers to generate and implement timing constraints (SDC).
• Conduct detailed timing analysis to verify designs meet specifications and performance metrics.
• Assist in constructing and refining workflows to improve efficiency in timing analysis processes.
• Collaborate with front-end and back-end teams to achieve the chip PPA target.

Conocimientos

Perl

Python

Tcl

Educación

Master’s degree or higher in Electronics Engineering, Computer Science, or related field

Descripción del empleo

Black Sesame Technologies is seeking fresh graduates to join as ASIC STA Engineers. This entry-level role focuses on timing closure, verification, constraints (SDC), and timing analysis to ensure chip performance and integrity.

You will work closely with front-end and back-end teams to drive PPA targets and learn the ASIC design flow. The position emphasizes learning, collaboration, and proactive problem-solving while contributing to innovative projects in ASIC timing analysis and design