Senior ASIC Design Engineer - Synthesis & Timing

Bitdeer Technologies Group; Singapore; On-site; SGD 90,000 - 150,000; Full time

Benefits offered by this job

Training & mentoring

Welfare benefits

Career growth opportunities

Job summary

Bitdeer Technologies Group is seeking an experienced IC Design Engineer in Singapore to drive synthesis, timing closure, and power optimization for ASIC designs. You will work closely with physical design teams on floorplanning, place & route, and timing bottlenecks, while applying low-power techniques and multi-clock domain awareness.

Proficiency in Verilog/SystemVerilog and industry-standard EDA tools is required, with exposure to NoC/interconnect architectures.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 3–7 years of IC design experience focusing on synthesis, timing closure, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus).

Responsibilities

• Synthesis and logic optimization for ASIC designs.
• STA, timing closure and CTS to optimize critical paths.
• Power and area optimization using low-power techniques and memory hierarchy optimization; collaborate with DFT engineers.
• Collaborate with physical design on floorplanning, place & route, timing bottlenecks.
• Formal verification and equivalence checking using Conformal, FormalPro, JasperGold.

Skills

Verilog/SystemVerilog

RTL-to-GDSII flow

EDA tools

Timing analysis

Clock tree synthesis

Multi-clock domains

Interconnect awareness (AXI/NoC)

Low-power design (UPF)

Scripting (TCL/Python)

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Conformal

FormalPro

JasperGold

Synopsys Design Compiler

Cadence Genus

PrimeTime

Innovus

Job description

Bitdeer Technologies Group is seeking an experienced IC Design Engineer in Singapore to drive synthesis, timing closure, and power optimization for ASIC designs. You will work closely with physical design teams on floorplanning, place & route, and timing bottlenecks, while applying low-power techniques and multi-clock domain awareness.

Proficiency in Verilog/SystemVerilog and industry-standard EDA tools is required, with exposure to NoC/interconnect architectures.