Image Signal Processing (ISP) RTL Design Engineer

Uni Connect; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

Uni Connect in Singapore is seeking an Image Signal Processing RTL Design Engineer to implement ISP algorithms in hardware using Verilog, SystemVerilog and/or SystemC, with emphasis on performance and efficiency.

You will define ISP HW architecture, verify at ISP and digital levels, optimize for gate count and low power, and drive ISP design activities in close collaboration with the algorithm team.

Qualifications

• Minimum MSEE, or BSEE, or equivalent.
• Experience with CMOS image sensors and ISP.
• Proficiency in SystemVerilog/SystemC and Catapult HLS tools.
• Strong debugging and problem-solving skills.
• Good communication and interpersonal abilities.
• Result oriented and adaptable to change.

Responsibilities

• Implement ISP algorithms in hardware using Verilog/SystemVerilog and/or SystemC.
• Define ISP hardware architecture based on features and performance; estimate gate count and power.
• Verify logic at ISP and digital system levels.
• Optimize design for lower gate count and reduced power.
• Lead ISP design activities in close collaboration with the ISP algorithm team.

Skills

CMOS image sensor

ISP knowledge

Debugging

Communication

Problem-solving

Change management

Education

MSEE / BSEE or equivalent

Tools

SystemVerilog

SystemC

Catapult HLS

Job description

Image Signal Processing (ISP) RTL Design Engineer

Singapore, Singapore | Posted on 03/27/2025

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
  
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
  
• Verify Logic at ISP level and Digital System level
  
• Optimize Design for less gate count and low power consumption
  
• Drive ISP Design activities in close collaboration with ISP Algorithm Team
  

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
  
• Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
  
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
  
• Strong debugging and problem-solving skills
  
• Good communication and interpersonal skills
  
• Result oriented and embrace change behaviours