(Sr.) ISP RTL Design Manager

OMNIVISION; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading technology firm in Singapore is seeking an experienced Digital Design Engineer to implement ISP algorithms and oversee the design architecture. You will lead and mentor a team of RTL design engineers, collaborating closely with various teams. Required qualifications include an MSEE or BSEE and over 7 years of experience in digital design. Expertise in System Verilog and project management is essential. This role presents an excellent opportunity to shape innovative designs in a dynamic environment.

Qualifications

• Minimum of 7+ years of Digital Design and verification related experience.
• Proven project management and people management experience.
• Experience in CMOS Image Sensor and image signal processing.

Responsibilities

• Implement ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC.
• Define ISP HW Architecture based on product features and performance.
• Verify Logic at ISP level and Digital System level.

Skills

Digital Design

Project Management

Team Leadership

Communication

Education

MSEE or BSEE or equivalent

Tools

System Verilog

System C/C++

Catapult HLS tool

Job description

Responsibilities:

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
• Leading, supervising and mentoring a team of RTL design engineers

Requirements:

• Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience
• 3+ years project management / people management experience / skill
• Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Ability to lead teams and collaborate effectively with people in different functions
• Excellent time management skills to ensure timely completion of deliverables
• Good communication and interpersonal skills
• Result oriented and adaptable to changes