Senior ISP RTL Design Engineer – Low Power Focus

Uni Connect; Singapore; Presencial; SGD 60 000 - 90 000; Tempo integral

Resumo da oferta

Uni Connect in Singapore is seeking an Image Signal Processing RTL Design Engineer to implement ISP algorithms in hardware using Verilog, SystemVerilog and/or SystemC, with emphasis on performance and efficiency.

You will define ISP HW architecture, verify at ISP and digital levels, optimize for gate count and low power, and drive ISP design activities in close collaboration with the algorithm team.

Qualificações

• Minimum MSEE, or BSEE, or equivalent.
• Experience with CMOS image sensors and ISP.
• Proficiency in SystemVerilog/SystemC and Catapult HLS tools.
• Strong debugging and problem-solving skills.
• Good communication and interpersonal abilities.
• Result oriented and adaptable to change.

Responsabilidades

• Implement ISP algorithms in hardware using Verilog/SystemVerilog and/or SystemC.
• Define ISP hardware architecture based on features and performance; estimate gate count and power.
• Verify logic at ISP and digital system levels.
• Optimize design for lower gate count and reduced power.
• Lead ISP design activities in close collaboration with the ISP algorithm team.

Conhecimentos

CMOS image sensor

ISP knowledge

Debugging

Communication

Problem-solving

Change management

Formação académica

MSEE / BSEE or equivalent

Ferramentas

SystemVerilog

SystemC

Catapult HLS

Descrição da oferta de emprego

Uni Connect in Singapore is seeking an Image Signal Processing RTL Design Engineer to implement ISP algorithms in hardware using Verilog, SystemVerilog and/or SystemC, with emphasis on performance and efficiency.

You will define ISP HW architecture, verify at ISP and digital levels, optimize for gate count and low power, and drive ISP design activities in close collaboration with the algorithm team.