HBM Validation Tech Lead – Memory Systems

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD; Singapore; On-site; SGD 180,000 - 260,000; Full time

Job summary

Micron Technology, Inc. is seeking a seasoned MTS to lead HBM Component Validation, defining coverage strategy and driving zero-escape validation. You will mentor engineers, collaborate with Design, DV, Reliability, and Systems teams, and champion AI-enabled workflows across global sites.

The role demands deep DRAM/HBM expertise, strong leadership, and hands-on validation debug across high-speed memory platforms.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• 10+ years of memory semiconductor validation experience.
• Strong knowledge of DRAM and HBM architecture, operation, and design.
• Experience reading and debugging circuit schematics to locate failures.
• Proficiency in Python/C/C++, Verilog, and version control.
• Experience with ATE platforms and APG concepts.

Responsibilities

• Act as technical authority for HBM component validation and coverage strategy.
• Define validation methodologies across structural and functional test flows.
• Lead validation for new and high-risk features with cross-functional teams.
• Mentor engineers and provide leadership updates to management.
• Drive AI-enabled workflows to accelerate coverage analysis and debug.
• Collaborate with Design, DV, Reliability, and Systems teams on experiments.

Skills

Leadership

Problem solving

Cross-functional collaboration

Mentoring

Strong communication

Technical leadership

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Verilog

APG

Python

C/C++

Version control

Oscilloscopes / logic analyzers

Job description

Micron Technology, Inc. is seeking a seasoned MTS to lead HBM Component Validation, defining coverage strategy and driving zero-escape validation. You will mentor engineers, collaborate with Design, DV, Reliability, and Systems teams, and champion AI-enabled workflows across global sites.

The role demands deep DRAM/HBM expertise, strong leadership, and hands-on validation debug across high-speed memory platforms.