Design Verification Manager

OmniVision Technologies Singapore Pte. Ltd.; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

A leading technology company in Singapore seeks a Design Verification Manager to lead a verification team in developing advanced methodologies for SoC design. Key responsibilities include test plan execution and achieving zero defects. Applicants should have strong knowledge of SoC design principles, experience in UVM verification, and at least 10 years of relevant experience. Strong leadership and communication skills are essential, with a plus for experience in video processing.

Qualifications

• Strong knowledge of SoC design principles including IP block integration.
• Experience with test plan development and execution.
• Familiarity with EDA tools for ASIC verification.
• Highly disciplined and quality-minded approach.
• Excellent communication and team leadership abilities.
• Strong expertise in UVM verification methodology.
• Experience in video processing is a plus.

Responsibilities

• Lead a verification team developing state-of-the-art methodologies.
• Conduct thorough test plan reviews and execute on-time.
• Aim for zero-defects with smart verification approaches.

Skills

SoC design principles

UVM verification methodology

C programming

Python

team leadership

communication skills

Education

MSEE/BSEE in Electrical Engineering or Computer Engineering

Tools

EDA tools

Job description

About the job Design Verification Manager

Description

As a Design Verification Manager, you are expected to carry out the following responsibilities.

• Be in-charge of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
• Conduct thorough test plan reviews systematically and execute the plan on-time with high quality.
• Achieve zero-defect with the best and smartest approach to the large verification space.

Requirements

• Strong knowledge of SoC design principles, including IP block integration and system-level verification
• Experience with test plan development, execution, and analysis
• Familiarity with EDA tools and development flows for ASIC verification
• Highly disciplined, quality-minded, and highly driven for excellence.
• Excellent team leader and good communication skills.
• Strong expertise in UVM verification methodology.
• Experience in C and/or a scripting language such as python or perl.
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience.
• Experience in RTL design is a plus.
• Experience in video processing and video analytics is a plus.
• Passionate and strong in general programming is a plus.