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UST in Singapore is seeking a verification engineer to apply UVM, SystemVerilog, Verilog and SVA in challenging tasks. You will develop and implement state-of-the-art verification methodologies including co-simulation, system emulation, and mixed-mode simulation.
The role requires a Masters or Bachelors in Electrical or Computer Engineering and at least 3 years of relevant experience; proficient in Ethernet and familiar with SPI, UART, and I2C protocols; collaborate effectively to deliver