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OmniVision Technologies Singapore Pte. Ltd. is seeking a Sr./Staff Design Verification Engineer to join a passionate verification team.
You will advance state-of-the-art verification methodologies, spanning UVM, C/C++ co-simulation, system emulation, mixed-mode simulation, and formal verification, with a goal of zero defects. The role emphasizes strong programming skills, teamwork, and communication, with opportunities to handle higher responsibilities for Senior or Staff levels.
Position Overview:
As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple to achieve zero-defect with the best and smartest approach to the large verification space.
Requirements: