Senior/ IC Design Engineer (Design Verification)

AUREXIS TECH PTE. LTD.; Singapore; On-site; SGD 52,000 - 70,000; Full time

Job summary

AUREXIS TECH PTE. LTD. in Singapore invites a verification engineer to contribute to pre-silicon IP/ASIC/SoC verification. You will build SystemVerilog/UVM testbenches, develop constrained-random tests, and implement SVA assertions with strong coverage metrics.

You will debug, analyze results, and drive closure while collaborating across design teams. Familiarity with AI-assisted EDA tools will be advantageous for optimizing verification workflows.

Qualifications

• Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field.
• Hands-on experience in ASIC/SoC/IP verification using SystemVerilog and UVM.
• Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl.
• Experience with industry-standard EDA tools (Cadence or Synopsys).
• Familiarity with AI/ML-assisted EDA tools is a plus.

Responsibilities

• Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
• Build and maintain SystemVerilog/ UVM-based verification environments and testbenches.
• Develop directed and constrained-random tests, assertions(SVA), and functional coverage.
• Debug DUT issues, analyze simulation results, and drive verification closure.
• Collaborate with cross-functional teams throughout the design and verification lifecycle.
• Support regression automation and continuously improve verification methodologies.
• Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity.

Skills

Analytical thinking

Problem solving

Communication skills

Education

Bachelor's or Master's in Electrical/Electronic/Computer Engineering (or related field)

1 year of experience

Tools

SystemVerilog

UVM

Constrained-random verification

SVA (Assertions)

Functional coverage

Python scripting

Job description

Job Description

• Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
• Build and maintain SystemVerilog/ UVM-based verification environments and testbenches
• Develop directed and constrained-random tests, assertions(SVA), and functional coverage.
• Debug DUT issues, analyze simulation results, and drive verification closure.
• Collaborate with cross-functional teams throughout the design and verification lifecycle.
• Support regression automation and continuously improve verification methodologies.
• Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity.

Requirements

• Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field with at least 1 year of experience.
• Hands-on experience in ASIC/SoC/IP verification using SystemVerilog and UVM.
• Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl.
• Experience with industry-standard EDA tools (e.g., Cadence or Synopsys).
• Familiarity with AI/ML-assisted EDA tools or the use of generative AI to improve verification workflows is an advantage.
• Strong analytical, problem-solving, and communication skills.