Design Verification Engineer (Internship)

OMNIVISION; Singapore; On-site; SGD 60,000 - 120,000; Full time

Job summary

OMNIVISION is seeking a Design Verification Engineer to join a passionate verification team, developing state-of-the-art methodologies across UVM, C/C++ co-simulation, system emulation and formal verification. The goal is zero-defect with the best approaches to large verification space.

The candidate should have a strong background in Verilog/SystemVerilog and be proficient in programming, with optional experience in CNN/Transformer and NPU/GPU/DSP verification.

Qualifications

• Disciplined, quality-minded and driven for excellence.
• Excellent team player and strong communication skills.
• MSEE/BSEE in Electrical Engineering or Computer Engineering.
• Experience in UVM verification is a plus.
• Knowledge in CNN/Transformer DL algorithms is a plus.
• Experience in NPU/GPU/DSP verification is a plus.
• Experience in ARM or RISC-V processor systems is a plus.
• Passionate and strong in programming is a plus.
• Commit at least 6 months full time and preferably 9 months.
• Good understanding of signed/unsigned number systems and their operations.
• Strong knowledge of Verilog or SystemVerilog is required.

Responsibilities

• Develop and deploy state-of-the-art verification methodologies for complex designs.
• Pursue zero-defect verification with best approaches in verification space.
• Collaborate with verification team to push limits and ensure quality.

Skills

UVM

C/C++

SystemVerilog

CNN/Transformer

NPU/GPU/DSP

ARM/RISC-V

Programming

Education

MSEE/BSEE (Electrical/Computer Engineering)

Tools

ARM

RISC-V

Job description

Job Description

As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits - developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation and formal verification. The goal is simple - to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

• Disciplined, quality-minded, and highly driven for excellence
• Excellent team player and good communication skills
• MSEE/BSEE in Electrical Engineering or Computer Engineering
• Experience in UVM verification methodology is a plus
• Knowledge in deep learning algorithms such as CNN / Transformer is a plus
• Experience in NPU / GPU / DSP verification is a plus
• Experience in ARM or RISC-V processor systems is a plus
• Passionate and strong in general programming is a plus
• Commit at least 6 months full time and preferably 9 months
• Good understanding of signed and unsigned number system and their operations
• Strong knowledge of Verilog or system Verilog is required