Design Verification Engineer — UVM & SystemVerilog

BITDEER DEVELOPMENT PTE. LTD.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Benefits offered by this job

Welfare benefits and training

Job summary

Bitdeer Technologies Group in Singapore seeks a verified engineer to advance its ASIC verification efforts. You will apply UVM, SystemVerilog, Verilog, and SVA to develop and execute robust test plans, and collaborate with design and verification teams to ensure high-quality silicon.

You will work with Palladium Z1, HAPS, Zebu platforms and drive regression and coverage-driven verification across complex DUTs.

Qualifications

• Proficient in verification languages and methodologies (UVM/SystemVerilog).
• Strong RTL understanding and experience with verification test plans.
• Familiarity with EDA toolchains (Synopsys/Cadence/Siemens).

Responsibilities

• Apply UVM, SystemVerilog, Verilog, and SVA in verification tasks.
• Develop verification methodologies including UVM, co-simulation, and mixed-mode simulation.
• Contribute to projects requiring advanced verification tools (Palladium Z1, HAPS, Zebu).
• Collaborate with verification/design engineers to define test plans and stimulus.
• Run and maintain regression suites; improve coverage metrics.
• Document verification results and support sign-off.

Skills

UVM

SystemVerilog

RTL development

C/C++

Linux scripting

Education

Bachelor’s or Master’s degree in Electrical Engineering/Computer Engineering/Computer Science

Tools

Palladium Z1

HAPS

Zebu

Job description

Bitdeer Technologies Group in Singapore seeks a verified engineer to advance its ASIC verification efforts. You will apply UVM, SystemVerilog, Verilog, and SVA to develop and execute robust test plans, and collaborate with design and verification teams to ensure high-quality silicon.

You will work with Palladium Z1, HAPS, Zebu platforms and drive regression and coverage-driven verification across complex DUTs.