CPU RTL Design Engineer - Core Integration & Performance

Brightecs Innovation Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Brightecs Innovation Pte. Ltd. (BIP) in Singapore seeks a senior CPU architect and RTL lead to design high-performance CPU cores and IP blocks. You will define microarchitecture, implement RTL in Verilog/SystemVerilog, and collaborate across verification, synthesis, and backend teams to meet PPA targets.

You will contribute to pre- and post-tape-out debugging, integrate IPs, and help drive timing, power, and area optimizations while mentoring junior engineers in a fast-moving startup environment.

Qualifications

• Master's degree or higher in microelectronics or related field.
• Strong understanding of CPU architecture and memory hierarchy.
• Proficient in Verilog/SystemVerilog with RTL coding standards.
• Experience in RTL integration of large-scale SoCs or CPU subsystems.
• Familiar with front-end design flow: synthesis, STA, formal verification, and DFT.
• Good scripting skills (Tcl/Python/Perl).
• Strong cross-team communication.

Responsibilities

• Design and document microarchitecture of high-performance CPUs.
• Lead Verilog RTL design of core modules (ALU, pipeline, MMU, Cache).
• RTL integration of IPs and top-level wiring; resolve timing/power conflicts.
• Collaborate with verification to develop test benches and simulations.
• Support synthesis/backend to meet PPA targets; participate in timing closure.
• Assist in pre/post-tape-out debugging and pre-silicon sim.

Skills

CPU architecture

Verilog/SystemVerilog

RTL integration

Scripting (Tcl/Python/Perl)

Cross-team collaboration

Education

Master's degree or above in Microelectronics, Computer Science, Electronic Engineering, or related fields

Tools

AMBA AXI/AHB/APB

Job description

Brightecs Innovation Pte. Ltd. (BIP) in Singapore seeks a senior CPU architect and RTL lead to design high-performance CPU cores and IP blocks. You will define microarchitecture, implement RTL in Verilog/SystemVerilog, and collaborate across verification, synthesis, and backend teams to meet PPA targets.

You will contribute to pre- and post-tape-out debugging, integrate IPs, and help drive timing, power, and area optimizations while mentoring junior engineers in a fast-moving startup environment.