Lead Staff Design Engineer - Digital BE & PPA Expert

LANCESOFT PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

LANCESOFT PTE. LTD. seeks an Associate Staff Design Engineer to lead BE implementation for high-performance SoCs and ASICs, covering synthesis, STA, timing sign-off, UPF and low-power checks, plus PPA optimization.

You will own timing constraints, collaborate with RTL/DFT teams, drive EDA tool flows, and guide end-to-end physical design from RTL to GDSII across multiple corners, mentoring junior engineers along the way.

Qualifications

• Bachelor’s or Master’s degree in ECE/EEE/VLSI or related field.
• 9–10 years of ASIC physical design experience.
• Hands-on expertise with industry-standard EDA tools (Cadence/Synopsys).
• Strong synthesis, constraints, margins and timing analysis skills.
• Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS).
• Understanding of GDSII flows and sign-off requirements.
• Excellent problem-solving and communication skills.

Responsibilities

• Own STA execution for digital blocks and top-level designs.
• Lead end-to-end BE implementation flow from RTL to GDSII for complex SoCs.
• Develop timing constraints and perform timing sign-off across modes and corners.
• Generate and interpret timing reports; implement timing ECOs.

Skills

Synthesis

STA

Timing analysis

UPF/CPF

Power optimization

PPA optimization

ECOS

Team leadership

EDA tool flow

Education

Bachelor’s or Master’s degree in ECE, EEE, VLSI or related field

Tools

Cadence Genus

Cadence Innovus

Cadence Tempus

Cadence LEC/CLP

Synopsys ICC2

Fusion Compiler

PrimeTime

Job description

LANCESOFT PTE. LTD. seeks an Associate Staff Design Engineer to lead BE implementation for high-performance SoCs and ASICs, covering synthesis, STA, timing sign-off, UPF and low-power checks, plus PPA optimization.

You will own timing constraints, collaborate with RTL/DFT teams, drive EDA tool flows, and guide end-to-end physical design from RTL to GDSII across multiple corners, mentoring junior engineers along the way.