CPU Design Engineer (Design & RTL Integration)

Brightecs Innovation Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Brightecs Innovation Pte. Ltd. (BIP) in Singapore seeks a senior CPU architect and RTL lead to design high-performance CPU cores and IP blocks. You will define microarchitecture, implement RTL in Verilog/SystemVerilog, and collaborate across verification, synthesis, and backend teams to meet PPA targets.

You will contribute to pre- and post-tape-out debugging, integrate IPs, and help drive timing, power, and area optimizations while mentoring junior engineers in a fast-moving startup environment.

Qualifications

• Master's degree or higher in microelectronics or related field.
• Strong understanding of CPU architecture and memory hierarchy.
• Proficient in Verilog/SystemVerilog with RTL coding standards.
• Experience in RTL integration of large-scale SoCs or CPU subsystems.
• Familiar with front-end design flow: synthesis, STA, formal verification, and DFT.
• Good scripting skills (Tcl/Python/Perl).
• Strong cross-team communication.

Responsibilities

• Design and document microarchitecture of high-performance CPUs.
• Lead Verilog RTL design of core modules (ALU, pipeline, MMU, Cache).
• RTL integration of IPs and top-level wiring; resolve timing/power conflicts.
• Collaborate with verification to develop test benches and simulations.
• Support synthesis/backend to meet PPA targets; participate in timing closure.
• Assist in pre/post-tape-out debugging and pre-silicon sim.

Skills

CPU architecture

Verilog/SystemVerilog

RTL integration

Scripting (Tcl/Python/Perl)

Cross-team collaboration

Education

Master's degree or above in Microelectronics, Computer Science, Electronic Engineering, or related fields

Tools

AMBA AXI/AHB/APB

Job description

• Responsible for the microarchitecture design and documentation of high-performance CPUs; deeply understand CPU architecture and participate in the definition of key modules.


• Lead Verilog RTL code design: Use Verilog/SystemVerilog to complete the RTL coding and development of CPU core modules (e.g., ALU, pipeline control, MMU, Cache controller, etc.).


• Responsible for RTL integration: Integrate independent IPs/sub-modules at the RTL level, complete top-level wiring and bus interface docking, and resolve cross-module timing, area, and power conflicts during the integration process.


• Work closely with the verification team to provide test cases and Testbenches, participate in module-level and system-level simulations, and assist in locating and fixing functional defects.


• Cooperate with the synthesis and backend physical design teams to provide high-quality RTL code, participate in SDC constraint definition and timing closure optimization to ensure final PPA (Power, Performance, Area) targets are met.


• Participate in pre- and post-tape-out debugging, assist in locating and resolving issues in pre-silicon simulation and post-silicon testing.

Required Qualifications:

• Master's degree or above in Microelectronics, Computer Science, Electronic Engineering, or related fields.


• Solid theoretical foundation in CPU architecture, deep understanding of core concepts such as pipeline mechanisms, out-of-order execution, branch prediction, and memory hierarchy (Cache/DDR), with a systematic understanding of CPU design.


• Proficient in Verilog/SystemVerilog hardware description languages, with excellent RTL coding standards and an understanding of low‑power design and code synthesizability requirements.


• Rich experience in RTL integration, familiar with bus protocols such as AMBA AXI/AHB/APB; experience in RTL integration of large-scale SoCs or CPU subsystems is preferred.


• Familiar with the front‑end design flow, understanding concepts of logic synthesis, Static Timing Analysis (STA), formal verification, and DFT.


• Good scripting skills (e.g. Tcl/Python/Perl) to write automation scripts and improve integration efficiency.


• Strong cross‑team communication skills, able to collaborate efficiently with architecture, verification, and backend teams.

Bonus Points:

• Experience in RTL integration and tape‑out of successful high-performance CPUs, GPUs, or large‑scale SoC chips.


• Familiarity with DRAM and related memory controller design is preferred.


• Actual development experience with RISC‑V or ARM architecture CPUs is preferred.

About Us

Brightecs Innovation Pte. Ltd. (BIP) is a private limited company incorporated in Singapore, founded in September 2025. As a newly established, technology-oriented startup, our core business is currently focused on silicon IP for intelligent computing.

At the core of our operations is our R&D center, Superam Academy of Semiconductor Research (Superam), a fabless chip research institution also based in Singapore. It specializes in high-end semiconductor IP services, offering diverse IP solutions and standard cell libraries for advanced CMOS technologies by employing Design-Technology-Co-Optimization (DTCO) technology. We enable our customers to achieve full optimization of Power, Performance, and Area (PPA) when designing on foundries' unique processes.

As our business continues to grow, BIP is committed to expanding its capabilities and scope into broader areas of technology innovation. We invite talented professionals to join us on this exciting journey. For more company information, please visit www.bipsuperam.com.

Why Join BIP

At BIP, you will be a founding contributor to something extraordinary. We are a young, passionate team driven by curiosity and a shared ambition to push the boundaries of technology. Here, your ideas matter, your contributions are visible, and your growth is limited only by your ambition. As we expand into new frontiers, we invite you to grow with us, take on challenges that inspire you, and help shape the future from day one. Ready to make a real impact?