SoC Design Engineer - End-to-End Chip & Verification

RICORE TECHNOLOGY PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

RICORE TECHNOLOGY PTE. LTD. in Singapore seeks a hands‑on SoC Design Engineer to contribute across architecture, RTL front‑end, verification and backend stages.

You will work with cross‑functional teams to define high‑performance architectures, optimise performance, power and area, and support post‑layout silicon bring‑up. The role requires 3+ years of end‑to‑end SoC design experience, proficiency with CHI/AXI/AMBA protocols, and hands‑on experience with RISC‑V or ARM cores.

Qualifications

• Bachelor's degree in Computer Architecture, Microelectronics, Electronics, Telecommunications or related field.
• Minimum 3 years hands-on SoC chip design experience with end-to-end tape-out track-record.
• Proficient in bus protocols CHI, AXI3/4/5, AHB, APB and ACE.
• Solid experience in PPA design and optimisation for high‑performance SoC designs.
• Hands-on experience with RISC‑V or ARM architectures in design & verification.
• Experience with Lint, CDC and Synthesis tools/flows is required.
• IP integration experience (DDR, PCIe, USB, Ethernet, UFS, SDIO) is a strong plus.

Responsibilities

• Participate in architecture design, collaborating with cross‑functional teams to define high‑performance specs.
• Contribute to front‑end design including module RTL, clock & reset, low‑power design, NoC bus, SoC integration.
• Conduct PPA evaluation and optimisation for modules and subsystems.
• Support Design Verification teams on module‑ and system‑level SoC verification activities.
• Engage in chip back‑end iterations, including performance and power analyses.
• Participate in post‑layout simulation, silicon bring‑up and production ramp‑up activities.

Job description

RICORE TECHNOLOGY PTE. LTD. in Singapore seeks a hands‑on SoC Design Engineer to contribute across architecture, RTL front‑end, verification and backend stages.

You will work with cross‑functional teams to define high‑performance architectures, optimise performance, power and area, and support post‑layout silicon bring‑up. The role requires 3+ years of end‑to‑end SoC design experience, proficiency with CHI/AXI/AMBA protocols, and hands‑on experience with RISC‑V or ARM cores.