Senior SoC Design Engineer — RTL & Verification

Silicon Labs Careers; Singapore; On-site; SGD 100,000 - 156,000; Full time

Job summary

Silicon Labs seeks a senior engineer to design block architectures for digital circuits and to drive SoC integration across cross-functional teams. You will implement RTL, verify IP blocks, and contribute to the development of mixed-signal verification and firmware validation for edge connectivity SoCs.

Responsibilities include architectural design, IP integration, and documentation for reference manuals and datasheets.

Qualifications

• Experience designing block architectures for digital circuits.
• Deep understanding of interfaces and block requirements.
• Ability to partition designs and implement RTL.
• Collaborate with cross-functional teams to develop requirements.
• Develop and verify SoC infrastructure and IP integration.

Responsibilities

• Design block architecture and digital circuits.
• Integrate digital blocks/IP into SoC.
• Develop SoC infrastructure such as bus matrix, memory interfaces, clocking, power management.
• Verify mixed-signal and RF IP and perform block-level verification.
• Develop embedded firmware to validate SoC integration.
• Create reference manuals and datasheet material.

Skills

RTL coding

Block architecture

SoC integration

Firmware development

Verification

Documentation

Tools

COSIMULATION

Job description

Silicon Labs seeks a senior engineer to design block architectures for digital circuits and to drive SoC integration across cross-functional teams. You will implement RTL, verify IP blocks, and contribute to the development of mixed-signal verification and firmware validation for edge connectivity SoCs.

Responsibilities include architectural design, IP integration, and documentation for reference manuals and datasheets.