Foundation IP Engineer

Cognitive Design Technology Pvt Ltd; Singapore; On-site; SGD 90,000 - 180,000; Full time

Job summary

Cognitive Design Technology, founded in 2007, is a leading technology solution provider with focus on Embedded Systems, Semiconductor, CAD, MEMS and Nanotechnology. We seek an experienced Memory Design Engineer to work on architecture, design, compiler development, characterization, and silicon validation of embedded SRAM and Register File IPs for ultra-low-power SoCs.

You will collaborate with architecture, physical design, product engineering, foundry, EDA vendors, and silicon validation teams

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Electronics, or related discipline.
• Experience developing embedded SRAM or Register File IP for advanced 12nm FINFET technologies and below.
• Hands-on experience with SRAM compiler development and configurable memory generation.

Responsibilities

• Design ultra-low power embedded SRAM and Register File IPs for advanced SoC products.
• Develop and enhance SRAM compiler architectures supporting multiple memory configurations, banking schemes and redundancy options.
• Design and optimize memory peripheral circuits such as sense amplifiers, write drivers, decoders, word-line drivers, pre-charge circuits, Read/write assist circuits, redundancy and repair logic
• Optimize memory designs for Area, Performance, Leakage power, Dynamic power, yield and manufacturability. Correlate simulation and characterization results with silicon measurements and production test data.
• Analyze low-voltage failure mechanisms including read disturb, write failure, read/write margins, retention failures and process variation effects
• Drive memory yield improvement through silicon debug, characterization analysis, and design optimization.
• Develop automation scripts using Python, Tcl, or Perl to improve compiler generation, characterization efficiency, regression, and design productivity.
• Collaborate with Memory architecture teams, Physical design, Timing and STA teams, DFT/BIST engineers, Product and test engineering, Foundry partners and EDA vendors
• Support memory IP integration into SoC products from architecture through production release.
• Document methodologies, design guidelines, characterization results, and silicon learnings.

Skills

SRAM architecture

Compiler design

Memory circuit design

Low-voltage SRAM

Python scripting

Tcl scripting

Perl scripting

Cadence tools

Education

Bachelor's/Master's/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

HSPICE

Cadence Liberate MX

Monte Carlo simulations

Job description

Cognitive Design Technology, founded in 2007, is a leading technology solution provider based in India. Specializing in advanced technology areas such as Embedded Systems, Semiconductor, CAD, MEMS, and Nanotechnology, the company offers a comprehensive suite of products, training, design services, and consultancy. Our solutions cater to industries including VLSI, Microelectronics, Solar, LED, RF/Digital ASIC, Analog Mixed Signal Design, CMOS Process, IC Packaging, and more. Through partnerships with world leaders in these technologies, we strive for customer satisfaction by providing complete and competitive solutions.

Exp:12+Years

JobType:Full-time

Scope

We are seeking an experienced Memory Design Engineer to work on the architecture, design, compiler development, characterization, and silicon validation of embedded SRAM and Register File (RF) IPs for ultra-low-power SoCs. The ideal candidate will possess strong expertise in SRAM compiler development, custom memory circuit design, timing and power characterization, silicon correlation, and production-quality memory IP delivery. This role requires close collaboration with architecture, physical design, product engineering, foundry, EDA vendors, and silicon validation teams to develop highly optimized embedded memories operating across conventional, near-threshold, and sub-threshold voltage ranges. This role is critical in ensuring robust memory operation across extreme low-voltage conditions, aligned with SPOT principles.

Responsibilities

• Design ultra-low power embedded SRAM and Register File IPs for advanced SoC products.
• Develop and enhance SRAM compiler architectures supporting multiple memory configurations, banking schemes and redundancy options.
• Design and optimize memory peripheral circuits such as sense amplifiers, write drivers, decoders, word-line drivers, pre-charge circuits, Read/write assist circuits, redundancy and repair logic
• Optimize memory designs for Area, Performance, Leakage power, Dynamic power, yield and manufacturability. Correlate simulation and characterization results with silicon measurements and production test data.
• Analyze low-voltage failure mechanisms including read disturb, write failure, read/write margins, retention failures and process variation effects
• Drive memory yield improvement through silicon debug, characterization analysis, and design optimization.
• Develop automation scripts using Python, Tcl, or Perl to improve compiler generation, characterization efficiency, regression, and design productivity.
• Collaborate with Memory architecture teams, Physical design, Timing and STA teams, DFT/BIST engineers, Product and test engineering, Foundry partners and EDA vendors
• Support memory IP integration into SoC products from architecture through production release.
• Document methodologies, design guidelines, characterization results, and silicon learnings.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Electronics, or related discipline.
• Strong understanding of SRAM architecture, compiler design, and custom memory circuit design.
• Proven experience developing embedded SRAM or Register File IP for advanced 12nm FINFET technologies and below.
• Hands-on experience with SRAM compiler development and configurable memory generation.
• Strong expertise in custom memory characterization and production-quality Liberty (.lib) generation.
• Deep knowledge of bit-cell operation, sense amplifier design, read/write assist techniques, low-voltage SRAM operation, process variation analysis, timing and power characterization
• Experience with Cadence Virtuoso, Spectre, HSPICE or equivalent SPICE simulators, Cadence Liberate MX and Monte Carlo simulations
• Familiarity with memory compiler architecture and IP delivery flows.
• Experience supporting silicon bring-up, characterization, debug, and production qualification.
• Knowledge of memory redundancy, repair algorithms, ECC, and MBIST integration is highly desirable.
• Strong scripting skills in Python, Tcl, Perl, or equivalent programming languages.
• Excellent analytical, debugging, communication, and cross-functional collaboration skills.