[2027 Internship] Memory Design Automation Intern

MediaTek Research Lab Inc.; Singapore; On-site; SGD 13,000 - 20,000; Full time

Job summary

MediaTek invites an internship candidate to join its Memory Design Automation team in Singapore. You will contribute to robust memory development and the automation flow for Memory Compiler projects, collaborating with a global team across advanced technology nodes.

The role focuses on data analysis, verification, timing, and QA tasks related to SRAM compiler tooling, offering hands-on experience in high-performance memory design.

Qualifications

• Bachelor’s or Master’s degree in Electrical and Electronic Engineering, Computer Engineering, or Computer Science.
• Multi-tasking capability and strong self-driven characteristics.
• Proficient with Perl, Shell, Python, and C/C++.
• Knowledge of machine learning frameworks is an added advantage.
• Strong interpersonal skills to work with a multi-cultural team.

Responsibilities

• Work on memory design automation, SRAM/ROM related tasks.
• Assist in physical verification (DRC/ERC/LVS/ANT) on SRAM compiler.
• Assist in timing, power, and noise simulations on SRAM compiler.
• Develop QA checks and automation for SRAM compiler.

Skills

Multi-tasking

Self-driven

Interpersonal skills

Education

Bachelor’s / Master’s Degree in Electrical and Electronic Engineering/Computer Engineering/Computer Science

Tools

Perl

Shell

Python

C/C++

Machine learning framework

Job description

[2027 Internship] Memory Design Automation Intern

Category Chip Design

Location Singapore

Experience No Work Expe.

Job Description

At MediaTek's Memory Design Automation team, we work seamlessly with worldwide memory design team to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as internship student for the delivery of robust memory and development of Memory Compiler automation flow.

What’s in it for you?

• Work closely with team to improve data mining and data analysis tool specifically on SRAM compiler’s parameter.
• Responsible for physical verification (DRC/ERC/LVS/ANT) on SRAM compiler.
• Responsible for timing, power and noise’s spice simulation on SRAM compiler.
• Responsible for QA check and development on SRAM compiler.

#LI-WC1

Main Requirements and Qualifications

[What you will bring]

• Bachelor’s /Master’s Degree in Electrical and Electronic Engineering/Computer Engineering/Computer Science
• Multi-task capability and strong self-driven characteristics
• Proficient with Perl, Shell, Python, C/C++ languages, knowledge with machine learning framework and infrastructure is an added advantage
• Strong interpersonal skills to work with team members with multi-cultural environment
• Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage