[2027 Internship] NPU Physical Implementation Intern

Mediatek Singapore Pte Ltd; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Mediatek Singapore Pte Ltd is seeking a specialist in NPU physical implementation to script and automate flows, and to design data mining processes for existing NPU designs. The role involves providing actionable recommendations to improve PPA efficiency from RTL to GDS.

The ideal candidate will have strong Python/Perl scripting ability, experience with NPU verification, and familiarity with SystemVerilog and SV compliant tools to drive verification and implementation across the NPU stack.

Qualifications

• Bachelor’s/Master’s Degree in a relevant field.
• Strong Python/Perl scripting skills.
• Experience with Neural Processing Unit concepts and silicon verification.
• Familiar with assertion-based verification (SVA) and SystemVerilog.

Responsibilities

• Scripting and flow automation for NPU Physical Implementation.
• Design data mining for existing NPU designs and provide recommendations for future PPA improvements.

Skills

Python

Perl

Scripting

NPU familiarity

Communication

Education

Bachelor's degree

Master's degree

Tools

ICC2/FC

Cadence

Magma

SystemVerilog

Job description

Job Description

[What’s in it for you?]

• Scripting and flow automation for NPU Physical Implementation
• Design the system to do data mining for all existing NPU design and Provide recommendations for later new NPU Physical Implementation best PPA recipe

#LI-WC1

Main Requirements and Qualifications

1. [What you will bring]
2. Bachelor’s/Master’s Degree in
3. Good communication and scripting skills like Python/Perl
4. Knowledge in Neural Processing Unit Familiarity, Silicon Debug and/or Functional/Direct Test Verification
5. Familiar with assertion-based verification (SVA) & System Verilog language
6. Knowledge in Processor verification, FPGA verification and/or Formal verification
7. Familiar with Synopsys ICC2/FC (preferred) or Cadence or Magma tools from netlists to GDS is a plus
8. Knowledge in NPU/GPU/CPU processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification) is a plus
9. Knowledge of high-speed/low power IP and custom circuit design is a plus
10. Familiar with power noise and reliability tools such as Redhawk and Voltus