[2027 Internship] Physical Verification Software CAD Intern

Mediatek Singapore Pte Ltd; Singapore; On-site; SGD 13,000 - 20,000; Part time

Job summary

Mediatek Singapore Pte Ltd is seeking a motivated student for hands-on experience in physical verification of chip tape-out. You will work with experienced engineers to learn DRC processes, layout tooling, and scripting to automate tasks. Mentors will guide you while you contribute to real-world tape-out activities.

The role emphasizes independent work, cross-team collaboration, and critical thinking as you gain exposure to full-chip construction and backend closure dynamics.

Qualifications

• Pursuing a degree in Electrical/Electronics/CS Engineering and able to work independently.
• Strong drive to learn and pick up new things in a fast-paced environment.
• Good communication and ability to collaborate across teams.
• Willingness to explore unfamiliar territory and seek innovative solutions.
• Demonstrated critical thinking when facing challenging problems.
• IC layout experience and scripting knowledge are a plus but not required.

Responsibilities

• Execute design rule checks on real chip design.
• Debug issues related to design rule checks during full chip integration.
• Do basic reporting on physical verification issues.
• Basic project management and project risk assessment reporting.
• Basic scripting automation to streamline workflows.

Skills

Cross-team collaboration

Independent work

Critical thinking

Communication

Learning mindset

Education

Pursuing Electrical/Electronics/CS Engineering degree

Tools

Laker

Calibre

Job description

Job Description

When you join us, you'll work alongside with experienced engineers who'll mentor and guide you. You will be involved in:

• Execute design rule checks on real chip design
• Debug real issues related to design rule checks happening at full chip integration
• Do basic reporting on physical verification issues
• Basic project management/project risk assessment reporting
• Basic scripting automation

Learning Outcomes: You will be able to

• Be familiar with linux environment
• Deep knowledge of Physical Verification in chip tape-out operations
• Understand and be exposed to the process of Full chip construction

o from individual IPs (IO/Analog/digital), necessary physical structures (eg. Sealring, mask alignment marker, clamp cells), dummy generation etc.

• Hands on experience with layout tool (Synopsys: Laker etc.)
• Hands on experience executing Design rule checks (Mentor Graphics: Calibre)
• Hands on debugging real chip issues related to physical verification
• Experience some basic project management
• Experience the bustle of backend closure of a real product tapeout
• Hands on experience in scripting with tcl/python/csh
• Experience real dynamics in cross team collaboration

Main Requirements and Qualifications

1. Pursuing a degree in Electrical/Electronics/Computer Science Engineering
2. Must be an independent worker and have a strong drive to learn and pick up new things
3. Able to communicate well and handle cross team collaboration
4. Be willing to explore unfamiliar territory and try to seek innovative solutions to existing or new problems
5. Able to demonstrate critical thinking when faced with difficult situations
6. Having IC layout experience and scripting knowledge is a plus but not a necessary skill