[2027 Internship] NPU Physical Implementation Intern

MediaTek; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

MediaTek in Singapore seeks an experienced engineer to drive NPU physical implementation through scripting, automation, and data-driven design decisions. You will mine existing NPU designs and propose optimised PPA strategies for next-generation cycles.

Candidates should have strong Python/Perl scripting, NPU familiarity, and verification knowledge across processor/FPGA/formal methods, plus proficiency with SVA/SystemVerilog and IC tools (ICC2/FC, Cadence, Magma).

Qualifications

• Bachelor's or master's degree in a relevant field.
• Strong scripting skills in Python or Perl.
• Experience with NPU familiarity, silicon debugging and verification.
• Familiar with SVA/SystemVerilog language.
• Experience in processor, FPGA or formal verification.
• Knowledge of IC design tools (Synopsys ICC2/FC, Cadence, Magma).
• Understanding RTL-to-GDS flow and power-reduction methods.
• Familiar with power/noise reliability tools such as Redhawk and Voltus.

Responsibilities

• Scripting and flow automation for NPU Physical Implementation.
• Design the system to do data mining for existing NPU designs and provide recommendations for future NPU Physical Implementation PPA.

Skills

Python

Perl

NPU familiarity

Silicon Debug

Functional/Direct Test Verification

SystemVerilog (SVA)

Processor verification

FPGA verification

Formal verification

RTL-to-GDS flow

Power reduction flows

Redhawk

Voltus

Education

Bachelor's/Master's Degree

Tools

Synopsys ICC2/FC

Cadence

Magma

Redhawk

Voltus

Job description

Job Description

• Scripting and flow automation for NPU Physical Implementation
• Design the system to do data mining for all existing NPU design and Provide recommendations for later new NPU Physical Implementation best PPA recipe

Main Requirements and Qualifications

• [What you will bring]
• Bachelor's/Master's Degree in
• Good communication and scripting skills like Python/Perl
• Knowledge in Neural Processing Unit Familiarity, Silicon Debug and/or Functional/Direct Test Verification
• Familiar with assertion-based verification (SVA) & System Verilog language
• Knowledge in Processor verification, FPGA verification and/or Formal verification
• Familiar with Synopsys ICC2/FC (preferred) or Cadence or Magma tools from netlists to GDS is a plus
• Knowledge in NPU/GPU/CPU processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification) is a plus
• Knowledge of high-speed/low power IP and custom circuit design is a plus
• Familiar with power noise and reliability tools such as Redhawk and Voltus