(Staff/Sr. Staff) NPU Design Engineer

OMNIVISION; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

A leading semiconductor company in Singapore is seeking an experienced designer for NPU projects. The role requires over 8 years of digital design expertise, including substantial SoC design experience and prior completion of NPU designs. Responsibilities include developing design specifications, microarchitecture design, and RTL coding using Verilog/System Verilog. Ideal candidates will possess strong leadership skills, a background in algorithms, and be team players passionate about excellence in engineering.

Qualifications

• 8+ years of digital design with 2-3 years of SoC design experience.
• Completion of at least one cycle of NPU design.
• Disciplined, quality-minded, driven for excellence.
• Experience leading teams of at least 3-4 people.

Responsibilities

• Develop design requirements for an NPU based on system specifications.
• Model performance of the NPU module and data throughput.
• Microarchitecture design and RTL coding using Verilog/System Verilog.
• Understand mathematics of convolution operators.

Skills

Digital design

SoC design experience

Microarchitecture design

RTL coding with Verilog/System Verilog

Power, timing, area analysis

Team leadership

Communication skills

Programming

Education

MSEE/BSEE in Electrical Engineering or Computer Engineering

Tools

UVM verification methodology

Job description

Responsibilities

1. Develop design requirements for an NPU based on system level specifications.
2. Being part of modelling the performance of the NPU module and its data transaction throughput.
3. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
4. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
5. Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
6. Optimizing micro-architecture design for low power and area is required.
7. Work closely with verification engineers to ensure comprehensive testing and debug any issues.
8. Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
9. Collaborate with software teams to assist in compiler and toolchain development and their debugging.
10. Produce clear and concise design documentation.

Requirements

1. 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
2. At least one cycle of NPU design completion experience is required.
3. Hands on experience in digital design is a must.
4. Preferably has led a team of at least 3 to 4 people in the past at the capacity of a design lead.
5. Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
6. Experience in synthesis, with analysis of power, timing and area.
7. Disciplined, quality-minded, and highly driven for excellence.
8. Excellent team player and good communication skills.
9. MSEE/BSEE in Electrical Engineering or Computer Engineering.
10. Understanding of convolution operator and number system is required.
11. Candidates with relevant experience would be offered as Senior, taking on higher responsibilities.
12. Experience in UVM verification methodology is a plus.
13. A plus to have SoC design experience.
14. Experience with optimizing micro-architectures for low-power and low-area is a plus.
15. Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
16. Experience with past design experience with NPU / GPU / DSP design is a plus.
17. Experience with ARM or RISC-V processor systems is a plus.
18. Being passionate and proficient at general programming is a plus.