(Staff/Sr. Staff) NPU Design Engineer

OmniVision Technologies Singapore Pte. Ltd.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

OmniVision Technologies Singapore Pte. Ltd. is seeking an experienced NPU Design Engineer (Staff/Sr.

Staff) to translate system specs into detailed design requirements and practical RTL blocks. You will drive microarchitecture decisions, optimize for PPA, and collaborate with verification and software teams to ensure robust designs. Ideal candidates have 8+ years in digital design with SoC exposure, hands-on RTL experience, and leadership of a small team.

Qualifications

• 8+ years of digital design with some SoC experience preferred.
• At least one NPU design completion experience required.
• Hands-on digital design experience a must.
• Possess leadership experience managing a small team.

Responsibilities

• Develop design requirements from system specs.
• Model performance and data throughput for NPU module.
• RTL coding for NPU sub-blocks in Verilog/SystemVerilog.
• Analyze convolution formats and number systems.
• Estimate and optimize PPA (performance/power/area).
• Lead microarchitecture optimization for low power/area.
• Collaborate with verification engineers for testing.
• Support integration, lint/timing/CDC checks.
• Coordinate with software teams on compiler/toolchain debugging.
• Produce design documentation.

Skills

Digital design

RTL coding

Verilog/SystemVerilog

Microarchitecture

Team leadership

Convolution math

Power/Area optimization

Communication

C/C++ familiarity

Education

MSEE/BSEE in Electrical or Computer Engineering

Tools

Verilog

SystemVerilog

UVM

Job description

About the job (Staff/Sr. Staff) NPU Design Engineer

Responsibilities

• Develop design requirements of an NPU given system level specifications.
• Being part of modelling the performance of the NPU module and its data transaction throughput.
• Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
• Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
• Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
• Optimizing micro-architecture design for low power and area is required.
• Work closely with verification engineers to ensure comprehensive testing and debug issues.
• Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
• Collaborate with software teams to assist in compiler and toolchain development and their debugging.
• Produce clear and concise design documentation.

Requirements

• 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
• At least one cycle of NPU design completion experience is required.
• Hands on in digital design experience is a must.
• Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
• Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
• Experience in synthesis, with analysis of power, timing and area.
• Disciplined, quality-minded, and highly driven for excellence.
• Excellent team player and good communication skills.
• MSEE/BSEE in Electrical Engineering or Computer Engineering.
• Understanding of convolution operator and number system is required.
• Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
• Experience in UVM verification methodology is a plus.
• A plus to have SoC design experience.
• Experience with optimizing micro-architectures for low-power and low-area is a plus.
• Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
• Experience with past design experience with NPU / GPU / DSP design is a plus.
• Experience with ARM or RISC-V processor systems is a plus.
• Passionate and strong in general programming is a plus.