Senior RTL Engineer - SoC Design & Tape-out Expert

Capgemini; Odivelas; Híbrido; EUR 55 000 - 75 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health insurance

Life insurance

Hybrid work model

Career growth programs

Training and certifications

Resumo da oferta

Capgemini Engineering in Portugal is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out. You will define microarchitectures for complex SoCs, implement RTL in Verilog/SystemVerilog/VHDL, and collaborate across Verification, Synthesis, STA, and DFT teams.

The role emphasizes timing closure, low-power techniques, and automation scripting, with a hybrid work model and opportunities across national and international projects.

Qualificações

• Bachelor’s or Master’s in Electrical or Computer Engineering or related field.
• 6+ years in RTL/ASIC/SoC/VLSI design.
• Strong Verilog, SystemVerilog and/or VHDL knowledge.
• Experience with microarchitecture definition and complex digital design.
• Knowledge of SoC methodologies and integration.
• Experience with Lint, CDC, and Low Power methodologies.
• Solid synthesis and STA understanding.
• Familiarity with ARM/RISC-V/x86 CPU architectures.
• Proficiency in Python or similar scripting languages.

Responsabilidades

• Perform feasibility studies to support system architecture and interface specs.
• Define and develop microarchitectures for complex digital blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Execute RTL quality checks, including Lint, CDC, and Low Power verification.
• Develop timing constraints and support synthesis and timing closure activities.
• Collaborate with Verification, Synthesis, STA, Physical Design, and DFT teams.
• Support design bring-up, integration and tape-out activities.
• Create automation scripts and design flows to improve efficiency.
• Participate in technical reviews and continuous improvement initiatives.

Conhecimentos

RTL design

ASIC/SoC

Verilog/SystemVerilog

VHDL

Synthesis

Static Timing Analysis

Lint/CDC

Low Power design

CPU architectures (ARM/RISC-V/x86)

Python scripting

Formação académica

Bachelor’s or Master’s in Electrical or Computer Engineering

Ferramentas

Python

Descrição da oferta de emprego

Capgemini Engineering in Portugal is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out. You will define microarchitectures for complex SoCs, implement RTL in Verilog/SystemVerilog/VHDL, and collaborate across Verification, Synthesis, STA, and DFT teams.

The role emphasizes timing closure, low-power techniques, and automation scripting, with a hybrid work model and opportunities across national and international projects.