Rtl Engineer

Capgemini Engineering; Vila Nova da Barquinha; Híbrido; EUR 55 000 - 85 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health and life insurance

Referral program

Hybrid work

Training & certifications

International projects

Great office locations

Resumo da oferta

A Capgemini Engineering, líder global em serviços de engenharia, busca um Engenheiro RTL Sênior para conduzir o design digital desde a definição da arquitetura até o tape-out. Você definirá microarquiteturas, implementará RTL em Verilog/SystemVerilog/VHDL e garantirá timing e qualidade com equipes multidisciplinares.

Desempenhe-se na íntegra com práticas de verificação e metodologias de Low Power, colaborando com equipes de Verificação, Síntese, STA e Design Físico.

Qualificações

• Graduação em Engenharia Elétrica, Engenharia de Computação ou área relacionada.
• 6+ anos de experiência em RTL, ASIC, SoC ou design VLSI.
• Forte conhecimento de Verilog, SystemVerilog e/ou VHDL.
• Experiência comprovada em definição de microarquiteturas e desenvolvimento de designs digitais complexos.
• Compreensão de metodologias de SoC e integração.
• Experiência com Lint, CDC e metodologias de Low Power.
• Bom conhecimento de fluxos de síntese e STA.
• Familiaridade com arquiteturas de CPU (ARM, RISC-V, x86).
• Conhecimentos de linguagens de script (Python, Perl ou C).
• Conhecimento de metodologias de verificação e fluxos de design.

Responsabilidades

• Conduzir atividades de design digital desde definição da arquitetura até tape-out.
• Definir e desenvolver microarquiteturas para blocos digitais complexos e SoCs.
• Implementar RTL usando Verilog, SystemVerilog ou VHDL.
• Executar checks de RTL (Lint, CDC, Low Power).
• Desenvolver constraints de timing e apoiar síntese e timing closure.
• Colaborar com equipes de Verificação, Síntese, STA, Design Físico e DFT.
• Apoiar bring-up, integração e tape-out.
• Criar scripts de automação, fluxos de design e ferramentas de engenharia.
• Participar de revisões técnicas e iniciativas de melhoria contínua.

Conhecimentos

RTL

ASIC

SoC

VLSI

Verilog

SystemVerilog

VHDL

microarchitecture

Lint

CDC

Low Power

Synthesis

STA

CPU architectures

Python

Perl

C

verification methodologies

Formação académica

Bacharelado em Engenharia Elétrica/Computação

Mestrado em Engenharia Elétrica/Computação

Descrição da oferta de emprego

Descrição do cargo

CAPGEMINI ENGINEERING At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

YOUR ROLE

As a Senior RTL Engineer, you will be responsible for driving digital design activities from architecture definition through tape-out, ensuring the successful delivery of high-performance and power-efficient products.

In this role, you will:

Perform feasibility studies to support system architecture definition, requirements analysis, and interface specification.

Define and develop microarchitectures for complex digital blocks and SoCs.

Implement RTL designs using Verilog, SystemVerilog, or VHDL.

Execute RTL quality checks, including Lint, CDC, and Low Power verification.

Develop timing constraints and support synthesis and timing closure activities.

Collaborate closely with Verification, Synthesis, STA, Physical Design, and DFT teams to achieve functionality, performance, power, and area targets.

Support design bring-up, integration, and tape-out activities.

Create and maintain automation scripts, design flows, and engineering tools to improve development efficiency.

Participate in technical reviews and contribute to continuous improvement initiatives.

YOUR PROFILE

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

6+ years of experience in RTL, ASIC, SoC, or VLSI design.

Strong knowledge of Verilog, SystemVerilog, and/or VHDL.

Proven experience in microarchitecture definition and complex digital design development.

Solid understanding of SoC design methodologies and integration.

Hands-on experience with Lint, CDC, and Low Power design methodologies.

Good knowledge of synthesis flows and Static Timing Analysis (STA).

Familiarity with CPU architectures and instruction sets such as ARM, RISC-V, or x86.

Experience with scripting and programming languages such as Python, Perl, or C.

Understanding of verification methodologies and design flows.

Strong problem-solving skills and attention to detail.

Excellent communication skills and ability to work effectively in multicultural and multidisciplinary environments.

What You'll Love About Working Here

Join a multicultural and inclusive team environment.

Enjoy a supportive atmosphere promoting work life balance.

Hybrid work.

Your career growth is central to our mission. Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.

Access valuable training and certifications in cutting edge technologies.

Engage in exciting national and international projects.

Health and life insurance.

Referral program with bonuses for talent recommendations.

Great office locations.

About Capgemini

Capgemini is an AI-powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people. With our strong heritage of nearly 60 years, we are a responsible and diverse group of 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering and business operations.