Senior ASIC Physical Design Engineer – Hybrid & Growth

Capgemini; Lisboa; Hybrid; EUR 65,000 - 90,000; Full time

Benefits offered by this job

Health and life insurance

Hybrid work

Career growth programs

Training and certifications

International projects

Job summary

Capgemini Engineering in Lisbon is seeking a Senior Physical Design Engineer to drive the implementation flow for complex ASICs. The role covers floorplanning, placement, CTS, routing, timing analysis, and sign-off across 10nm and below technology nodes.

You will develop ECOs, perform physical verification (DRC/LVS/EM/IR/Antenna), and collaborate with multidisciplinary teams while advancing low-power design methodologies and automation scripting in Perl, TCL, and Python.

Qualifications

• 6+ years of experience in Physical Design or ASIC implementation.
• Experience with 10nm or below nodes.
• Experience with 500K–1M+ instances.
• Proficiency with STA, DRC, LVS, EM/IR, and timing closure.
• Scripting and automation with Perl, TCL, Python, Makefile.

Responsibilities

• Lead physical design across the implementation flow from floorplanning to tape-out.
• Perform floorplanning, placement, CTS, routing, and power planning.
• Drive timing analysis, timing closure, and signal integrity analysis.
• Generate and implement functional and timing ECOs; verify with FPV, EM/IR, DRC/LVS/Antenna checks.
• Support sign-off and tape-out; collaborate with multidisciplinary teams.

Skills

Floorplanning experience

Timing closure

Signal integrity knowledge

Strong problem-solving

English communication

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

Synopsys PD tools

Cadence PD tools

Perl

TCL

Python

Makefile

Job description

Capgemini Engineering in Lisbon is seeking a Senior Physical Design Engineer to drive the implementation flow for complex ASICs. The role covers floorplanning, placement, CTS, routing, timing analysis, and sign-off across 10nm and below technology nodes.

You will develop ECOs, perform physical verification (DRC/LVS/EM/IR/Antenna), and collaborate with multidisciplinary teams while advancing low-power design methodologies and automation scripting in Perl, TCL, and Python.