Senior Physical Design Engineer

Capgemini; Lisboa; Hybrid; EUR 65,000 - 90,000; Full time

Benefits offered by this job

Health and life insurance

Hybrid work

Career growth programs

Training and certifications

International projects

Job summary

Capgemini Engineering in Lisbon is seeking a Senior Physical Design Engineer to drive the implementation flow for complex ASICs. The role covers floorplanning, placement, CTS, routing, timing analysis, and sign-off across 10nm and below technology nodes.

You will develop ECOs, perform physical verification (DRC/LVS/EM/IR/Antenna), and collaborate with multidisciplinary teams while advancing low-power design methodologies and automation scripting in Perl, TCL, and Python.

Qualifications

• 6+ years of experience in Physical Design or ASIC implementation.
• Experience with 10nm or below nodes.
• Experience with 500K–1M+ instances.
• Proficiency with STA, DRC, LVS, EM/IR, and timing closure.
• Scripting and automation with Perl, TCL, Python, Makefile.

Responsibilities

• Lead physical design across the implementation flow from floorplanning to tape-out.
• Perform floorplanning, placement, CTS, routing, and power planning.
• Drive timing analysis, timing closure, and signal integrity analysis.
• Generate and implement functional and timing ECOs; verify with FPV, EM/IR, DRC/LVS/Antenna checks.
• Support sign-off and tape-out; collaborate with multidisciplinary teams.

Skills

Floorplanning experience

Timing closure

Signal integrity knowledge

Strong problem-solving

English communication

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

Synopsys PD tools

Cadence PD tools

Perl

TCL

Python

Makefile

Job description

# Senior Physical Design EngineerVNG - Cais Gaia, Fundão, Lisboa - ExpoApply for this job* Permanent* Experienced Professionals* Products & Systems Engineering* ID 584942-en\\_GB## CAPGEMINI ENGINEERINGAt Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.## YOUR ROLEAs a **Senior Physical Design Engineer**, you will be responsible for driving physical design activities across the implementation flow, from floorplanning through sign-off and tape-out, working on complex designs and advanced technology nodes.In this role, you will:* Perform block and full-chip Physical Design using advanced technology nodes (10nm and below).* Perform floorplanning, partitioning, power planning, placement, Clock Tree Synthesis (CTS), routing, and optimization.* Drive timing analysis and timing closure, including signal integrity and noise analysis.* Generate and implement functional and timing ECOs.* Perform physical verification activities, including Formal Verification, EM/IR, DRC, LVS, Antenna, and ERC analysis and fixes.* Work on Low Power design implementation and related methodologies.* Develop scripts for clock skew analysis, critical path analysis, I/O interfaces, and constraint partitioning and budgeting.* Support sign-off and tape-out activities.* Work closely with multidisciplinary engineering teams throughout the design implementation and closure process.## YOUR PROFILE* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.* 6+ years of experience in Physical Design or related ASIC implementation activities.* Experience with advanced technology nodes of 10nm and below.* Experience working on complex designs with 500K to 1M+ instances.* Strong hands-on experience with Synopsys and/or Cadence Physical Design and timing analysis tools.* Solid experience in floorplanning, power planning, placement, CTS, routing, and design optimization.* Knowledge of synthesis flows and DFT scan insertion and coverage.* Strong knowledge of Static Timing Analysis (STA), signal integrity, and timing closure.* Experience with functional and timing ECO generation and implementation.* Hands-on experience with EM/IR, DRC, LVS, Antenna, and ERC analysis and fixes.* Experience with sign-off and tape-out activities.* Proficiency in scripting languages and automation tools such as Perl, TCL, Python, and Makefile.* Experience with top-level floorplanning and pin assignment is considered a plus.* Good command of English, both written and spoken.* Strong problem-solving skills, technical autonomy, and ability to work effectively in multidisciplinary environments.## WHAT YOU’LL LOVE ABOUT WORKING HERE* Join a multicultural and inclusive team environment.* Enjoy a supportive atmosphere promoting work life balance.* Hybrid work.* Your career growth is central to our mission. Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.* Access valuable training and certifications in cutting edge technologies.* Engage in exciting national and international projects.* Health and life insurance.* Referral program with bonuses for talent recommendations.* Great office locations.## ABOUT CAPGEMINICapgemini is the business transformation partner for enterprises in the age of AI. We help organizations imagine and build an intelligent, sustainable future, combining AI, technology and human ingenuity to transform how they operate, innovate and grow. With unique end-to-end capabilities spanning strategy, technology, engineering and intelligent operations, we bring together deep industry expertise and market-leading capabilities in AI, cloud and data to turn ambition into measurable business outcomes at scale. Supported by a robust ecosystem of partners and nearly 60 years of expertise, Capgemini is a responsible and diverse global organization of over 410,000 team members in more than 50 countries.