Analog Layout Engineer (FinFET technology)

Capgemini; Vila Nova de Gaia; Presencial; EUR 60 000 - 90 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Hybrid work

Health and life insurance

Referral program with bonuses

Great office locations

Training and certifications

Resumo da oferta

Capgemini Engineering in Porto is seeking an experienced Analog Layout Engineer with strong FinFET expertise. You will design and optimize analog layouts, ensure DRC/LVS compliance, and collaborate with circuit designers to enhance performance and reliability.

Key tasks include EM/IR analysis, parasitic mitigation, and implementation of matching techniques. Flexibility for hybrid work and international projects is offered.

Qualificações

• Minimum 5 years of hands-on FinFET layout design for Analog IP development.
• Strong knowledge of LDE effects (WPE, STI, LOD) and mitigation strategies.
• Proficiency in Cadence Virtuoso, Calibre and PVS.
• Familiarity with parasitic extraction flows and correlation techniques.
• Understanding of reliability mechanisms (BTI, HCI) and guard-banding in layout.
• Experience with advanced-node design rules and color-aware layout.
• Knowledge of EM/IR verification methodologies and sign-off flows.
• Ability to automate layout tasks using SKILL or Python scripts.

Responsabilidades

• Develop analog layouts for circuits such as amplifiers, references, bias blocks and data converters in FinFET nodes.
• Apply best practices for DRC/LVS closure, including advanced tips and tricks for efficient debugging.
• Perform EM/IR analysis and implement layout changes to meet reliability targets.
• Address parasitic effects through careful routing, shielding, and post-extraction corrections.
• Implement matching techniques (common-centroid, interdigitation, dummy devices) for precision circuits.
• Collaborate with circuit designers to optimize layout for performance and yield.
• Ensure compliance with color-aware routing and multi-patterning constraints (SADP/SAQP).

Conhecimentos

FinFET layout design

LDE effects

Cadence Virtuoso

Calibre

PVS

Parasitic extraction

Reliability mitigation (BTI, HCI)

Color-aware layout

EM/IR verification

SKILL scripting

Python scripting

Advanced-node design rules

Color-aware routing

Ferramentas

Cadence Virtuoso

Calibre

PVS

Descrição da oferta de emprego

CAPGEMINI ENGINEERING

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

YOUR ROLE

We are seeking an experienced Analog Layout Engineer with strong expertise in FinFET technology. The candidate will design and implement analog layouts for advanced nodes, ensuring compliance with design rules and optimizing for performance, reliability, and manufacturability.

Key responsibilities:

• Develop analog layouts for circuits such as amplifiers, references, bias blocks and data converters in FinFET nodes
• Apply best practices for DRC/LVS closure, including advanced tips and tricks for efficient debugging
• Perform EM/IR analysis and implement layout changes to meet reliability targets
• Address parasitic effects through careful routing, shielding, and post-extraction corrections
• Implement matching techniques (common-centroid, interdigitation, dummy devices) for precision circuits
• Collaborate with circuit designers to optimize layout for performance and yield
• Ensure compliance with color-aware routing and multi-patterning constraints (SADP/SAQP)

YOUR PROFILE

• Minimum 5 years of hands-on experience in FinFET layout design for Analog IP development
• Strong knowledge of LDE effects (WPE, STI, LOD) and mitigation strategies
• Proficiency in industry-standard EDA tools (Cadence Virtuoso, Calibre, PVS)
• Familiarity with parasitic extraction flows and correlation techniques
• Understanding of reliability mechanisms (BTI, HCI) and guard-banding in layout
• Experience with advanced-node design rules and color-aware layout
• Knowledge of EM/IR verification methodologies and sign-off flows
• Ability to automate layout tasks using SKILL or Python scripts

WHAT YOU'LL LOVE ABOUT WORKING HERE

• Join a multicultural and inclusive team environment.
• Enjoy a supportive atmosphere promoting work life balance.
• Hybrid work.
• Your career growth is central to our mission.
• Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.
• Access valuable training and certifications in cutting edge technologies.
• Engage in exciting national and international projects.
• Health and life insurance.
• Referral program with bonuses for talent recommendations.
• Great office locations.

ABOUT CAPGEMINI

Capgemini is an AI‑powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people. With our strong heritage of nearly 60 years, we are a responsible and diverse group of 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering and business operations.