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Capgemini Engineering is seeking an experienced Analog Layout Engineer in Portugal to design and implement analog layouts for FinFET nodes. You will ensure design rule compliance, optimize for performance, reliability, and manufacturability, and collaborate with circuit designers.
The role requires 5+ years in FinFET layout, proficiency with Cadence Virtuoso, Calibre, and PVS, and a strong grasp of EM/IR analysis. Hybrid work is offered along with health insurance and professional growth.
Capgemini Engineering is seeking an experienced Analog Layout Engineer in Portugal to design and implement analog layouts for FinFET nodes. You will ensure design rule compliance, optimize for performance, reliability, and manufacturability, and collaborate with circuit designers.
The role requires 5+ years in FinFET layout, proficiency with Cadence Virtuoso, Calibre, and PVS, and a strong grasp of EM/IR analysis. Hybrid work is offered along with health insurance and professional growth.