Senior DFT Lead, Semiconductors | Hybrid & Growth Upskilling

Capgemini Engineering

Kraków

Híbrido

PLN 180 000 - 260 000

Tempo integral

Há 8 dias

Uma candidatura completa num minuto

Currículo e carta de apresentação personalizados, prontos a enviar.

Ultrapassa os filtros ATS

Vantagens oferecidas por esta oferta de emprego

Medicover medical care
Private life insurance
Sports card
Capgemini Helpline

Resumo da oferta

Capgemini Engineering is seeking a senior DFT engineer to drive DFT implementation for advanced SOCs. You will work across design, verification and test teams to optimize scan chains, ATPG patterns, JTAG and MBIST/LBIST, while mentoring a multi-site DFT team and supporting silicon bring-up.

You will apply scripting in Perl/Tcl/Python to automate workflows, collaborate with physical design to resolve timing issues, and continuously improve test coverage and efficiency in a hybrid Kraków

Qualificações

  • 6+ years of hands-on experience with DFT and test flows for large SOCs.
  • Strong knowledge of DFT techniques: JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500, MBIST/LBIST.
  • Hands-on in Perl/Tcl/Python scripting.

Responsabilidades

  • DFT implementation inline with existing test methodology for advanced process nodes.
  • Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST.
  • Collaborate with physical design to resolve timing constraints and debug timing issues.
  • Verify DFT circuitry and interface with IPs; debug timing simulations.
  • Improve DFT KPIs: test coverage and pattern efficiency; hierarchical retargeting.
  • Lead a multilocational team of DFT engineers; silicon bring-up and fault analysis.

Conhecimentos

DFT
JTAG
ATPG
MBIST/LBIST
Scripting

Ferramentas

Synopsys DFT Compiler
Tetramax
VCS
Tessent
Modus/Encounter

Descrição da oferta de emprego

Capgemini Engineering is seeking a senior DFT engineer to drive DFT implementation for advanced SOCs. You will work across design, verification and test teams to optimize scan chains, ATPG patterns, JTAG and MBIST/LBIST, while mentoring a multi-site DFT team and supporting silicon bring-up.

You will apply scripting in Perl/Tcl/Python to automate workflows, collaborate with physical design to resolve timing issues, and continuously improve test coverage and efficiency in a hybrid Kraków

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