Senior DFT Engineer

Commit; Warszawa; Presencial; PLN 395 000 - 526 000; Tempo integral

Resumo da oferta

Commit is hiring a Senior DFT Engineer in Europe to own Design-for-Test on customer SoCs end-to-end: DFT architecture, scan/ATPG, memory BIST, boundary scan, pattern validation and production test hand-off.

You will lead end-to-end DFT flow from concept to tape-out and production, applying hands-on experience with industry tools and standards to deliver robust test solutions for complex SoCs.

Qualificações

• Minimum 3 years of hands-on DFT experience — must. Senior-level profiles preferred.
• DFT methodologies: scan, ATPG, at-speed test, memory BIST, I/O DFT.
• Scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ fault models; test-coverage improvement.
• DFT DRC analysis and coverage debug with Synopsys DFT Compiler / TestMAX (TetraMAX) / SpyGlass DFT or equivalent Siemens (Mentor) Tessent tools.
• Memory BIST — Tessent MBIST.
• Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6 and IEEE 1500 (formerly P1500).
• Hands‑on design and implementation of DFT features.
• End‑to‑end DFT flow ownership: concept - tape‑out - production.
• Gate‑level simulation setup and runs (pattern validation).
• Formal equivalence checking.
• Perl / Tcl / UNIX scripting for flow automation.

Conhecimentos

DFT methodologies

Scan insertion

ATPG

Memory BIST

I/O DFT

Gate-level simulation

Formal equivalence checking

Perl / Tcl / UNIX scripting

Formação académica

BSc in Electrical Engineering

Ferramentas

Synopsys DFT Compiler

TestMAX (TetraMAX)

SpyGlass DFT

Tessent (MBIST/Boundary Scan)

Descrição da oferta de emprego

We are hiring a Senior DFT Engineer in Europe to own Design-for-Test on customer SoCs end-to-end: DFT architecture, scan/ATPG, memory BIST, boundary scan, pattern validation and production test hand-off.

The company provides end-to-end ASIC and COT design and turnkey manufacturing services to fabless companies and OEMs building advanced SoCs. Its offering covers architecture, RTL-to-GDSII implementation, analog/mixed-signal design, and productization through silicon, package, and test. Working across process nodes from 180nm to 2nm, it has completed over 350 tape-outs since 1986.

Requirements:

Must-Have Requirements:

• BSc in Electrical Engineering from a recognized university.
• Minimum 3 years of hands-on DFT experience — must. Senior-level profiles preferred.
• DFT methodologies: scan, ATPG, at-speed test, memory BIST, I/O DFT.
• Scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ fault models; test-coverage improvement.
• DFT DRC analysis and coverage debug with Synopsys DFT Compiler / TestMAX (TetraMAX) / SpyGlass DFT or equivalent Siemens (Mentor) Tessent tools.
• Memory BIST — Tessent MBIST.
• Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6 and IEEE 1500 (formerly P1500).
• Hands‑on design and implementation of DFT features.
• End‑to‑end DFT flow ownership: concept - tape‑out - production.
• Gate‑level simulation setup and runs (pattern validation).
• Formal equivalence checking.
• Perl / Tcl / UNIX scripting for flow automation.

Nice to Have

• Broader Siemens Tessent experience (ScanPro / TestKompress, LBIST) beyond MBIST.
• Advanced-node experience (7nm and below).
• Python for flow automation.