Senior RTL & SoC Digital Design Lead (Hybrid)

Capgemini Engineering

Katowice

Hybrid

PLN 240,000 - 480,000

Full time

8 days ago

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Job summary

Capgemini Engineering in Katowice, Poland seeks a Digital Design expert to join our semiconductor-focused team building the next generation of SoCs and digital IPs. You will tackle complex design challenges in a cutting-edge environment with collaboration across verification, physical design, and architecture groups.

The role requires hands-on RTL design experience and strong Verilog/VHDL skills; SystemVerilog is a plus.

Qualifications

  • 7+ years of hands-on experience in digital design across SoCs.
  • Strong knowledge of Verilog and/or VHDL; SystemVerilog is a plus.
  • Proven experience in RTL design, uArch development, and functional specs.

Responsibilities

  • Lead Functional Specification Development for advanced digital systems
  • Design and implement Microarchitecture (uArch) for high-performance blocks
  • Perform RTL Debugging, ensuring design correctness and efficiency
  • Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks
  • Collaborate with verification, physical design, and architecture teams
  • (Bonus) Contribute to Front-End Synthesis and optimization
  • (Nice to have) Experience working on SoC-level integration and design
  • (Nice to have) Apply Power Optimization Techniques for energy-efficient designs

Skills

Digital design
Verilog/VHDL
SystemVerilog
RTL design
Linting/CDC debugging
SoC design
Communication

Education

Bachelor's degree in EE/ECE/CE/CS
MS or PhD preferred

Tools

Cadence Genus
Synopsys DC
Fusion Compiler

Job description

Capgemini Engineering in Katowice, Poland seeks a Digital Design expert to join our semiconductor-focused team building the next generation of SoCs and digital IPs. You will tackle complex design challenges in a cutting-edge environment with collaboration across verification, physical design, and architecture groups.

The role requires hands-on RTL design experience and strong Verilog/VHDL skills; SystemVerilog is a plus.

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