Senior RTL & SoC Designer — Hybrid

Capgemini Engineering; Lublin; Hybrid; PLN 180,000 - 280,000; Full time

Job summary

Capgemini Engineering Poland is seeking a Senior Digital Design Expert to join a cutting-edge semiconductor team. You will lead RTL development, uArch concepts, and collaborate across verification, physical design, and architecture teams.

You will work with Cadence Genus, Synopsys DC, and Fusion Compiler to implement high-performance digital blocks, optimize power, and ensure design correctness. A strong background in Verilog/VHDL and SystemVerilog is essential.

Qualifications

• 7+ years of hands-on experience in digital design.
• Strong knowledge of Verilog and/or VHDL.
• Familiarity with SystemVerilog is a plus.
• Experience with tools like Cadence Genus, Synopsys Design Compiler (DC), or Fusion Compiler is a plus.
• Proven experience in RTL design, uArch development, and functional specs.
• Deep understanding of linting tools, CDC methodologies, and debugging flows.
• Familiarity with synthesis tools and SoC design is a strong plus.
• Bachelor's degree in EE, ECE, CE, CS, or a related field required; MS or PhD highly desired.
• Excellent communication and collaboration skills.

Responsibilities

• Lead Functional Specification Development for advanced digital systems
• Design and implement Microarchitecture (uArch) for high-performance blocks
• Perform RTL Debugging, ensuring design correctness and efficiency
• Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks
• Collaborate with verification, physical design, and architecture teams
• (Bonus) Contribute to Front-End Synthesis and optimization
• (Nice to have) Experience working on SoC-level integration and design
• (Nice to have) Apply Power Optimization Techniques for energy-efficient designs

Skills

Digital design

RTL design

Verilog/VHDL

SystemVerilog

collaboration

debugging flows

communication

Education

Bachelor's degree in EE/ECE/CE/CS

MS or PhD desirable

Tools

Cadence Genus

Synopsys Design Compiler (DC)

Fusion Compiler

Job description

Capgemini Engineering Poland is seeking a Senior Digital Design Expert to join a cutting-edge semiconductor team. You will lead RTL development, uArch concepts, and collaborate across verification, physical design, and architecture teams.

You will work with Cadence Genus, Synopsys DC, and Fusion Compiler to implement high-performance digital blocks, optimize power, and ensure design correctness. A strong background in Verilog/VHDL and SystemVerilog is essential.