Senior DFT Engineer - End-to-End SoC Test (Europe)

Commit; Warszawa; On-site; PLN 395,000 - 526,000; Full time

Job summary

Commit is hiring a Senior DFT Engineer in Europe to own Design-for-Test on customer SoCs end-to-end: DFT architecture, scan/ATPG, memory BIST, boundary scan, pattern validation and production test hand-off.

You will lead end-to-end DFT flow from concept to tape-out and production, applying hands-on experience with industry tools and standards to deliver robust test solutions for complex SoCs.

Qualifications

• Minimum 3 years of hands-on DFT experience — must. Senior-level profiles preferred.
• DFT methodologies: scan, ATPG, at-speed test, memory BIST, I/O DFT.
• Scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ fault models; test-coverage improvement.
• DFT DRC analysis and coverage debug with Synopsys DFT Compiler / TestMAX (TetraMAX) / SpyGlass DFT or equivalent Siemens (Mentor) Tessent tools.
• Memory BIST — Tessent MBIST.
• Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6 and IEEE 1500 (formerly P1500).
• Hands‑on design and implementation of DFT features.
• End‑to‑end DFT flow ownership: concept - tape‑out - production.
• Gate‑level simulation setup and runs (pattern validation).
• Formal equivalence checking.
• Perl / Tcl / UNIX scripting for flow automation.

Skills

DFT methodologies

Scan insertion

ATPG

Memory BIST

I/O DFT

Gate-level simulation

Formal equivalence checking

Perl / Tcl / UNIX scripting

Education

BSc in Electrical Engineering

Tools

Synopsys DFT Compiler

TestMAX (TetraMAX)

SpyGlass DFT

Tessent (MBIST/Boundary Scan)

Job description

Commit is hiring a Senior DFT Engineer in Europe to own Design-for-Test on customer SoCs end-to-end: DFT architecture, scan/ATPG, memory BIST, boundary scan, pattern validation and production test hand-off.

You will lead end-to-end DFT flow from concept to tape-out and production, applying hands-on experience with industry tools and standards to deliver robust test solutions for complex SoCs.