DFT Lead, Semiconductors | Hybrid Role

Capgemini Engineering; Katowice; On-site; PLN 180,000 - 280,000; Full time

Job summary

Capgemini Engineering is seeking a senior DFT engineer in Poland to drive design-for-test and related verification for advanced SOCs. You will implement inline DFT, validate patterns, and work closely with the physical design team to resolve timing constraints.

The role requires extensive experience with DFT methodologies and tools, strong problem-solving skills, and the ability to lead a distributed team. Hybrid working options may apply.

Qualifications

• 6+ years hands-on experience with DFT and test flows in SOCs.
• Strong knowledge of JTAG, ATPG, yield learning, and MBIST/LBIST.
• Experience with major EDA tools (DFT, simulation, RTL checks).

Responsibilities

• DFT implementation inline with test methodology for advanced nodes.
• Perform top or block-level DFT insertion and pattern validation.
• Collaborate with physical design to resolve timing issues.
• Verify DFT circuitry and interface with IPs; debug timing simulations.
• Improve DFT KPIs: test coverage and pattern efficiency.
• Lead a multilocational DFT engineering team.

Skills

DFT and test flows

Scripting (Perl/Tcl/Python)

Analytical and problem-solving

Hands-on with EDA flows

Team leadership potential

Tools

Synopsys DFT Compiler

Tetramax

VCS

Tessent

Modus/Encounter

Job description

Capgemini Engineering is seeking a senior DFT engineer in Poland to drive design-for-test and related verification for advanced SOCs. You will implement inline DFT, validate patterns, and work closely with the physical design team to resolve timing constraints.

The role requires extensive experience with DFT methodologies and tools, strong problem-solving skills, and the ability to lead a distributed team. Hybrid working options may apply.