Senior RTL/SoC Digital Design Lead (Hybrid)

Capgemini Engineering; Poznań; Hybrid; PLN 180,000 - 240,000; Full time

Benefits offered by this job

Medical care

Private life insurance

Wellbeing program

Hybrid work model

Job summary

Capgemini Engineering in Poznań is seeking a Digital Design expert to take on complex challenges in the semiconductor space. Join our cutting-edge team to help build the next generation of SoCs and digital IPs.

You will lead functional spec development, design microarchitecture, perform RTL debugging, and collaborate with verification, physical design, and architecture teams. A strong background in Verilog/VHDL and RTL design is required; SystemVerilog is a plus.

Qualifications

• 7+ years of hands-on experience in digital design.
• Strong knowledge of Verilog and/or VHDL.
• Familiarity with SystemVerilog is a plus.
• Experience with Cadence Genus, Synopsys DC, or Fusion Compiler is a plus.
• Proven RTL design, uArch development, and functional specs experience.
• Deep understanding of linting tools, CDC methodologies, and debugging flows.
• Familiarity with synthesis tools and SoC design is a plus.
• Bachelor's degree required; MS/PhD highly desirable.

Responsibilities

• Lead Functional Specification Development for advanced digital systems.
• Design and implement Microarchitecture (uArch) for high-performance blocks.
• Perform RTL Debugging, ensuring design correctness and efficiency.
• Run and analyze Lint Checks and CDC checks.
• Collaborate with verification, physical design, and architecture teams.
• Bonus: Contribute to Front-End Synthesis and optimization.
• Nice to have: SoC-level integration and design experience.
• Nice to have: Power optimization techniques for energy-efficient designs.

Skills

Digital design

Verilog/VHDL

SystemVerilog

RTL design

Linting/CDC

Synthesis tools

Communication skills

Education

Bachelor's degree in EE/CE/CS

MS or PhD preferred

Tools

Cadence Genus

Synopsys Design Compiler

Fusion Compiler

Job description

Capgemini Engineering in Poznań is seeking a Digital Design expert to take on complex challenges in the semiconductor space. Join our cutting-edge team to help build the next generation of SoCs and digital IPs.

You will lead functional spec development, design microarchitecture, perform RTL debugging, and collaborate with verification, physical design, and architecture teams. A strong background in Verilog/VHDL and RTL design is required; SystemVerilog is a plus.