Senior SoC Verification Engineer: Drive High-Impact Validation

Lattice Philippines; Philippines; On-site; PHP 1,200,000 - 2,100,000; Full time

Job summary

Lattice Semiconductor Philippines is seeking a Senior Verification Engineer to lead verification planning and regression for complex SoCs. You will develop SystemVerilog and C-based testbenches in UVM, verify blocks and sub-systems, and collaborate with design and software teams to meet tight project timelines.

Ideal candidates have 6–10 years in digital design verification, HDL/HVL expertise, and hands-on experience with major simulation tools.

Qualifications

• Develop verification plans with clear metrics and track progress.
• Create SystemVerilog and C-based testbenches in UVM environment.
• Verify design blocks, sub-systems, and full chip using assertions and randomized tests.

Responsibilities

• Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project.
• Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests.
• Understand specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment.
• Design and develop testbench components such as UVCs, BFMs and verification tools.
• Define and design verification regression environment.
• Perform functional coverage, RTL coverage, assertion coverage, and gate-level simulations.
• Collaborate with design engineers and SW developers to deliver high-quality SoC verification on aggressive schedules.

Skills

SystemVerilog

UVM

HDL languages

Verilog

Python

C

Debugging

Documentation

Education

Bachelor's degree in Computer Science or Electrical Engineering

Tools

Cadence IES/ XFEL or Xcelium

Synopsys VCS

Mentor Questa

Job description

Lattice Semiconductor Philippines is seeking a Senior Verification Engineer to lead verification planning and regression for complex SoCs. You will develop SystemVerilog and C-based testbenches in UVM, verify blocks and sub-systems, and collaborate with design and software teams to meet tight project timelines.

Ideal candidates have 6–10 years in digital design verification, HDL/HVL expertise, and hands-on experience with major simulation tools.