Lead Formal Verification Engineer - Drive Correctness

SiFive, Inc.; Hinoba-an; On-site; PHP 1,200,000 - 2,000,000; Full time

Job summary

SiFive is a pioneer of RISC‑V and is seeking a senior Formal Verification Engineer to join our hardware design team in the Philippines. You will lead formal verification efforts for digital blocks, develop test plans, and maintain FV environments in Chisel, aiming for robust, verifiable designs.

The ideal candidate has 8+ years in digital FV, strong knowledge of HDL (VHDL/Verilog/SystemVerilog), and hands-on experience with VC Formal or JasperGold, along with teamwork and clear communication

Qualifications

• 8+ years of experience in Formal Verification of Digital Hardware Design
• Extensive experience with Formal Abstraction Techniques and sign-off process
• Familiarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold
• Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ System Verilog
• Knowledge of Object-oriented Programming is a plus
• A keen interest in Processors and Digital systems
• Strong reasoning skills and excellent attention to detail
• Good inter-personal and teamwork skills!
• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Responsibilities

• Identify blocks suitable for applying Formal Verification
• Create Formal Test‑plan for blocks identifying properties to be implemented and sign‑off metrics
• Implementation and maintenance of Formal Verification environments in Chisel
• Applying various FV techniques to reduce complexity and prove correctness of DUT
• Debugging RTL to identify causes of failure scenarios
• Guide and train team members on effective usage of Formal Verification tools
• Develop/modify scripts to automate the verification process
• Review formal setups and proofs with design and verification teams
• Maintain and extend assertion libraries

Skills

Formal verification

HDL knowledge

Verilog/SystemVerilog

VC Formal

JasperGold

Object-oriented programming

Teamwork

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

VC Formal

JasperGold

Job description

SiFive is a pioneer of RISC‑V and is seeking a senior Formal Verification Engineer to join our hardware design team in the Philippines. You will lead formal verification efforts for digital blocks, develop test plans, and maintain FV environments in Chisel, aiming for robust, verifiable designs.

The ideal candidate has 8+ years in digital FV, strong knowledge of HDL (VHDL/Verilog/SystemVerilog), and hands-on experience with VC Formal or JasperGold, along with teamwork and clear communication